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Commit 2a709b01 authored by Gaurav Kohli's avatar Gaurav Kohli Committed by Puja Gupta
Browse files

soc: qcom: pil-q6v5: Add support for qdspv62.1.5 reset 



Update the reset sequence to support qdspv62-1-5 for MSMFALCON.
Also enable one more memory bank during reset sequence for MSMFALCON.

Change-Id: Ib0d27c13c0ebdfac629c1469c9a91a0b84d03640
Signed-off-by: default avatarGaurav Kohli <gkohli@codeaurora.org>
parent b17afbac

Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt

+1 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ Optional properties: 
				    current issue.

- qcom,qdsp6v61-1-1: Boolean- Present if the qdsp version is v61 1.1

- qcom,qdsp6v62-1-2: Boolean- Present if the qdsp version is v62 1.2

- qcom,qdsp6v62-1-5: Boolean- Present if the qdsp version is v62 1.5

- qcom,mx-spike-wa: Boolean- Present if we need to assert QDSP6 I/O clamp, memory

		    wordline clamp, and compiler memory clamp during MSS restart.

- qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10

drivers/soc/qcom/pil-q6v5.c

+13 −3
Original line number Diff line number Diff line
@@ -393,7 +393,7 @@ static int __pil_q6v55_reset(struct pil_desc *pil) 
	mb();

	udelay(1);



	if (drv->qdsp6v62_1_2) {

	if (drv->qdsp6v62_1_2 || drv->qdsp6v62_1_5) {

		for (i = BHS_CHECK_MAX_LOOPS; i > 0; i--) {

			if (readl_relaxed(drv->reg_base + QDSP6V62SS_BHS_STATUS)

			    & QDSP6v55_BHS_EN_REST_ACK)
@@ -493,7 +493,8 @@ static int __pil_q6v55_reset(struct pil_desc *pil) 
			 */

			udelay(1);

		}

	} else if (drv->qdsp6v61_1_1 || drv->qdsp6v62_1_2) {

	} else if (drv->qdsp6v61_1_1 || drv->qdsp6v62_1_2 ||

						drv->qdsp6v62_1_5) {

		/* Deassert QDSP6 compiler memory clamp */

		val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL);

		val &= ~QDSP6v55_CLAMP_QMC_MEM;
@@ -506,7 +507,13 @@ static int __pil_q6v55_reset(struct pil_desc *pil) 
		/* Turn on L1, L2, ETB and JU memories 1 at a time */

		val = readl_relaxed(drv->reg_base +

				QDSP6V6SS_MEM_PWR_CTL);

		for (i = 28; i >= 0; i--) {



		if (drv->qdsp6v62_1_5)

			i = 29;

		else

			i = 28;



		for ( ; i >= 0; i--) {

			val |= BIT(i);

			writel_relaxed(val, drv->reg_base +

					QDSP6V6SS_MEM_PWR_CTL);
@@ -668,6 +675,9 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) 
	drv->qdsp6v62_1_2 = of_property_read_bool(pdev->dev.of_node,

						"qcom,qdsp6v62-1-2");



	drv->qdsp6v62_1_5 = of_property_read_bool(pdev->dev.of_node,

						"qcom,qdsp6v62-1-5");



	drv->non_elf_image = of_property_read_bool(pdev->dev.of_node,

						"qcom,mba-image-is-not-elf");

drivers/soc/qcom/pil-q6v5.h

+1 −0
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ struct q6v5_data { 
	bool qdsp6v56_1_10;

	bool qdsp6v61_1_1;

	bool qdsp6v62_1_2;

	bool qdsp6v62_1_5;

	bool non_elf_image;

	bool restart_reg_sec;

	bool override_acc;