drm/nouveau/bus: add interfaces/helpers for sequencer (2984506f) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/gpu/drm/nouveau/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -44,6 +44,7 @@ nouveau-y += core/subdev/bios/xpio.o
		nouveau-y += core/subdev/bus/nv04.o
		nouveau-y += core/subdev/bus/nv31.o
		nouveau-y += core/subdev/bus/nv50.o
		nouveau-y += core/subdev/bus/nv94.o
		nouveau-y += core/subdev/bus/nvc0.o
		nouveau-y += core/subdev/clock/nv04.o
		nouveau-y += core/subdev/clock/nv40.o

drivers/gpu/drm/nouveau/core/engine/device/nv50.c

+10 −10

Original line number	Diff line number	Diff line
		@@ -166,7 +166,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		@@ -192,7 +192,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		@@ -218,7 +218,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		@@ -244,7 +244,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		@@ -270,7 +270,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		@@ -296,7 +296,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		@@ -322,7 +322,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		@@ -350,7 +350,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		@@ -377,7 +377,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		@@ -404,7 +404,7 @@ nv50_identify(struct nouveau_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;

drivers/gpu/drm/nouveau/core/include/subdev/bus.h

+12 −0

Original line number	Diff line number	Diff line
		@@ -11,6 +11,8 @@ struct nouveau_bus_intr {

		struct nouveau_bus {
		struct nouveau_subdev base;
		int (hwsq_exec)(struct nouveau_bus , u32 *, u32);
		u32 hwsq_size;
		};

		static inline struct nouveau_bus *
		@@ -36,6 +38,16 @@ nouveau_bus(void *obj)
		extern struct nouveau_oclass *nv04_bus_oclass;
		extern struct nouveau_oclass *nv31_bus_oclass;
		extern struct nouveau_oclass *nv50_bus_oclass;
		extern struct nouveau_oclass *nv94_bus_oclass;
		extern struct nouveau_oclass *nvc0_bus_oclass;

		/* interface to sequencer */
		struct nouveau_hwsq;
		int nouveau_hwsq_init(struct nouveau_bus , struct nouveau_hwsq *);
		int nouveau_hwsq_fini(struct nouveau_hwsq **, bool exec);
		void nouveau_hwsq_wr32(struct nouveau_hwsq *, u32 addr, u32 data);
		void nouveau_hwsq_setf(struct nouveau_hwsq *, u8 flag, int data);
		void nouveau_hwsq_wait(struct nouveau_hwsq *, u8 flag, u8 data);
		void nouveau_hwsq_nsec(struct nouveau_hwsq *, u32 nsec);

		#endif

drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c

0 → 100644

+145 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2013 Red Hat Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: Ben Skeggs <bskeggs@redhat.com>
		*/

		#include <subdev/timer.h>
		#include <subdev/bus.h>

		struct nouveau_hwsq {
		struct nouveau_bus *pbus;
		u32 addr;
		u32 data;
		struct {
		u8 data[512];
		u8 size;
		} c;
		};

		static void
		hwsq_cmd(struct nouveau_hwsq *hwsq, int size, u8 data[])
		{
		memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0]));
		hwsq->c.size += size;
		}

		int
		nouveau_hwsq_init(struct nouveau_bus pbus, struct nouveau_hwsq *phwsq)
		{
		struct nouveau_hwsq *hwsq;

		hwsq = phwsq = kmalloc(sizeof(hwsq), GFP_KERNEL);
		if (hwsq) {
		hwsq->pbus = pbus;
		hwsq->addr = ~0;
		hwsq->data = ~0;
		memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data));
		hwsq->c.size = 0;
		}

		return hwsq ? 0 : -ENOMEM;
		}

		int
		nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec)
		{
		struct nouveau_hwsq hwsq = phwsq;
		int ret = 0, i;
		if (hwsq) {
		struct nouveau_bus *pbus = hwsq->pbus;
		hwsq->c.size = (hwsq->c.size + 4) / 4;
		if (hwsq->c.size <= pbus->hwsq_size) {
		if (exec)
		ret = pbus->hwsq_exec(pbus, (u32 *)hwsq->c.data,
		hwsq->c.size);
		if (ret)
		nv_error(pbus, "hwsq exec failed: %d\n", ret);
		} else {
		nv_error(pbus, "hwsq ucode too large\n");
		ret = -ENOSPC;
		}

		for (i = 0; ret && i < hwsq->c.size; i++)
		nv_error(pbus, "\t0x%08x\n", ((u32 *)hwsq->c.data)[i]);

		*phwsq = NULL;
		kfree(hwsq);
		}
		return ret;
		}

		void
		nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data)
		{
		nv_debug(hwsq->pbus, "R[%06x] = 0x%08x\n", addr, data);

		if (hwsq->data != data) {
		if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {
		hwsq_cmd(hwsq, 5, (u8[]){ 0xe2, data, data >> 8,
		data >> 16, data >> 24 });
		} else {
		hwsq_cmd(hwsq, 3, (u8[]){ 0x42, data, data >> 8 });
		}
		}

		if ((addr & 0xffff0000) != (hwsq->addr & 0xffff0000)) {
		hwsq_cmd(hwsq, 5, (u8[]){ 0xe0, addr, addr >> 8,
		addr >> 16, addr >> 24 });
		} else {
		hwsq_cmd(hwsq, 3, (u8[]){ 0x40, addr, addr >> 8 });
		}

		hwsq->addr = addr;
		hwsq->data = data;
		}

		void
		nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data)
		{
		nv_debug(hwsq->pbus, " FLAG[%02x] = %d\n", flag, data);
		flag += 0x80;
		if (data >= 0)
		flag += 0x20;
		if (data >= 1)
		flag += 0x20;
		hwsq_cmd(hwsq, 1, (u8[]){ flag });
		}

		void
		nouveau_hwsq_wait(struct nouveau_hwsq *hwsq, u8 flag, u8 data)
		{
		nv_debug(hwsq->pbus, " WAIT[%02x] = %d\n", flag, data);
		hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
		}

		void
		nouveau_hwsq_nsec(struct nouveau_hwsq *hwsq, u32 nsec)
		{
		u8 shift = 0, usec = nsec / 1000;
		while (usec & ~3) {
		usec >>= 2;
		shift++;
		}

		nv_debug(hwsq->pbus, " DELAY = %d ns\n", nsec);
		hwsq_cmd(hwsq, 1, (u8[]){ 0x00 \| (shift << 2) \| usec });
		}

drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h

0 → 100644

+113 −0

Original line number	Diff line number	Diff line
		#ifndef __NVKM_BUS_HWSQ_H__
		#define __NVKM_BUS_HWSQ_H__

		#include <subdev/bus.h>

		struct hwsq {
		struct nouveau_subdev *subdev;
		struct nouveau_hwsq *hwsq;
		int sequence;
		};

		struct hwsq_reg {
		int sequence;
		bool force;
		u32 addr[2];
		u32 data;
		};

		static inline struct hwsq_reg
		hwsq_reg2(u32 addr1, u32 addr2)
		{
		return (struct hwsq_reg) {
		.sequence = 0,
		.force = 0,
		.addr = { addr1, addr2 },
		.data = 0xdeadbeef,
		};
		}

		static inline struct hwsq_reg
		hwsq_reg(u32 addr)
		{
		return hwsq_reg2(addr, addr);
		}

		static inline int
		hwsq_init(struct hwsq ram, struct nouveau_subdev subdev)
		{
		struct nouveau_bus *pbus = nouveau_bus(subdev);
		int ret;

		ret = nouveau_hwsq_init(pbus, &ram->hwsq);
		if (ret)
		return ret;

		ram->sequence++;
		ram->subdev = subdev;
		return 0;
		}

		static inline int
		hwsq_exec(struct hwsq *ram, bool exec)
		{
		int ret = 0;
		if (ram->subdev) {
		ret = nouveau_hwsq_fini(&ram->hwsq, exec);
		ram->subdev = NULL;
		}
		return ret;
		}

		static inline u32
		hwsq_rd32(struct hwsq ram, struct hwsq_reg reg)
		{
		if (reg->sequence != ram->sequence)
		reg->data = nv_rd32(ram->subdev, reg->addr[0]);
		return reg->data;
		}

		static inline void
		hwsq_wr32(struct hwsq ram, struct hwsq_reg reg, u32 data)
		{
		reg->sequence = ram->sequence;
		reg->data = data;
		if (reg->addr[0] != reg->addr[1])
		nouveau_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
		nouveau_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
		}

		static inline void
		hwsq_nuke(struct hwsq ram, struct hwsq_reg reg)
		{
		reg->force = true;
		}

		static inline u32
		hwsq_mask(struct hwsq ram, struct hwsq_reg reg, u32 mask, u32 data)
		{
		u32 temp = hwsq_rd32(ram, reg);
		if (temp != ((temp & ~mask) \| data) \|\| reg->force)
		hwsq_wr32(ram, reg, (temp & ~mask) \| data);
		return temp;
		}

		static inline void
		hwsq_setf(struct hwsq *ram, u8 flag, int data)
		{
		nouveau_hwsq_setf(ram->hwsq, flag, data);
		}

		static inline void
		hwsq_wait(struct hwsq *ram, u8 flag, u8 data)
		{
		nouveau_hwsq_wait(ram->hwsq, flag, data);
		}

		static inline void
		hwsq_nsec(struct hwsq *ram, u32 nsec)
		{
		nouveau_hwsq_nsec(ram->hwsq, nsec);
		}

		#endif