Merge "clk: msm: mdmfermium: Correct apc measure clocks for mdmfermium" (291e7403) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/clk/msm/clock-gcc-mdmfermium.c

+25 −73

Original line number	Diff line number	Diff line
		@@ -1508,30 +1508,6 @@ static struct measure_clk apc0_m_clk = {
		},
		};

		static struct measure_clk apc1_m_clk = {
		.c = {
		.ops = &clk_ops_empty,
		.dbg_name = "apc1_m_clk",
		CLK_INIT(apc1_m_clk.c),
		},
		};

		static struct measure_clk apc2_m_clk = {
		.c = {
		.ops = &clk_ops_empty,
		.dbg_name = "apc2_m_clk",
		CLK_INIT(apc2_m_clk.c),
		},
		};

		static struct measure_clk apc3_m_clk = {
		.c = {
		.ops = &clk_ops_empty,
		.dbg_name = "apc3_m_clk",
		CLK_INIT(apc3_m_clk.c),
		},
		};

		static struct measure_clk l2_m_clk = {
		.c = {
		.ops = &clk_ops_empty,
		@@ -1542,52 +1518,13 @@ static struct measure_clk l2_m_clk = {

		static void __iomem *meas_base;

		static struct mux_clk apss_debug_ter_mux = {
		.ops = &mux_reg_ops,
		.mask = 0x3,
		.shift = 8,
		MUX_SRC_LIST(
		{&apc0_m_clk.c, 0},
		{&apc1_m_clk.c, 1},
		{&apc2_m_clk.c, 2},
		{&apc3_m_clk.c, 3},
		),
		.base = &meas_base,
		.c = {
		.dbg_name = "apss_debug_ter_mux",
		.ops = &clk_ops_gen_mux,
		CLK_INIT(apss_debug_ter_mux.c),
		},
		};

		static struct mux_clk apss_debug_sec_mux = {
		.ops = &mux_reg_ops,
		.mask = 0x7,
		.shift = 12,
		MUX_SRC_LIST(
		{&apss_debug_ter_mux.c, 0},
		{&l2_m_clk.c, 1},
		),
		MUX_REC_SRC_LIST(
		&apss_debug_ter_mux.c,
		),
		.base = &meas_base,
		.c = {
		.dbg_name = "apss_debug_sec_mux",
		.ops = &clk_ops_gen_mux,
		CLK_INIT(apss_debug_sec_mux.c),
		},
		};

		static struct mux_clk apss_debug_pri_mux = {
		.ops = &mux_reg_ops,
		.mask = 0x3,
		.shift = 16,
		.mask = 0x7,
		.shift = 3,
		MUX_SRC_LIST(
		{&apss_debug_sec_mux.c, 0},
		),
		MUX_REC_SRC_LIST(
		&apss_debug_sec_mux.c,
		{&apc0_m_clk.c, 3},
		{&l2_m_clk.c, 2},
		),
		.base = &meas_base,
		.c = {
		@@ -1597,7 +1534,20 @@ static struct mux_clk apss_debug_pri_mux = {
		},
		};

		static struct clk_ops clk_ops_debug_mux;
		static int gcc_set_mux_sel(struct mux_clk *clk, int sel)
		{
		u32 regval;

		regval = readl_relaxed(GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
		regval &= 0x1FF;
		writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));

		if (sel == 0xFFFF)
		return 0;
		mux_reg_ops.set_mux_sel(clk, sel);

		return 0;
		}

		static struct measure_clk_data debug_mux_priv = {
		.cxo = &xo_clk_src.c,
		@@ -1608,10 +1558,11 @@ static struct measure_clk_data debug_mux_priv = {
		.status_reg = CLOCK_FRQ_MEASURE_STATUS,
		.base = &virt_bases[DEBUG_BASE],
		};

		static struct clk_ops clk_ops_debug_mux;
		static struct clk_mux_ops gcc_debug_mux_ops;
		static struct mux_clk gcc_debug_mux = {
		.priv = &debug_mux_priv,
		.ops = &mux_reg_ops,
		.ops = &gcc_debug_mux_ops,
		.offset = GCC_DEBUG_CLK_CTL,
		.mask = 0x1FF,
		.en_offset = GCC_DEBUG_CLK_CTL,
		@@ -1919,9 +1870,6 @@ static struct clk_lookup msm_clocks_measure[] = {
		CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),
		CLK_LIST(apss_debug_pri_mux),
		CLK_LIST(apc0_m_clk),
		CLK_LIST(apc1_m_clk),
		CLK_LIST(apc2_m_clk),
		CLK_LIST(apc3_m_clk),
		CLK_LIST(l2_m_clk),
		};

		@@ -1933,6 +1881,10 @@ static int msm_clock_debug_probe(struct platform_device *pdev)
		clk_ops_debug_mux = clk_ops_gen_mux;
		clk_ops_debug_mux.get_rate = measure_get_rate;

		gcc_debug_mux_ops = mux_reg_ops;
		gcc_debug_mux_ops.set_mux_sel = gcc_set_mux_sel;


		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
		if (!res) {
		dev_err(&pdev->dev, "Register base not defined\n");