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Commit 28853ac8 authored by Paulius Zaleckas's avatar Paulius Zaleckas
Browse files

ARM: Add support for FA526 v2 



Adds support for Faraday FA526 core. This core is used at least by:
Cortina Systems Gemini and Centroid family
Cavium Networks ECONA family
Grain Media GM8120
Pixelplus ImageARM
Prolific PL-1029
Faraday IP evaluation boards

v2:
- move TLB_BTB to separate patch
- update copyrights

Signed-off-by: default avatarPaulius Zaleckas <paulius.zaleckas@teltonika.lt>
parent bba7d0b9

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi 
tune-$(CONFIG_CPU_ARM922T)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM925T)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_ARM926T)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_FA526)	:=-mtune=arm9tdmi

tune-$(CONFIG_CPU_SA110)	:=-mtune=strongarm110

tune-$(CONFIG_CPU_SA1100)	:=-mtune=strongarm1100

tune-$(CONFIG_CPU_XSCALE)	:=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale

arch/arm/boot/compressed/head.S

+26 −0
Original line number Diff line number Diff line
@@ -459,6 +459,20 @@ __armv7_mmu_cache_on: 
		mcr	p15, 0, r0, c7, c5, 4	@ ISB

		mov	pc, r12



__fa526_cache_on:

		mov	r12, lr

		bl	__setup_mmu

		mov	r0, #0

		mcr	p15, 0, r0, c7, c7, 0	@ Invalidate whole cache

		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer

		mcr	p15, 0, r0, c8, c7, 0	@ flush UTLB

		mrc	p15, 0, r0, c1, c0, 0	@ read control reg

		orr	r0, r0, #0x1000		@ I-cache enable

		bl	__common_mmu_cache_on

		mov	r0, #0

		mcr	p15, 0, r0, c8, c7, 0	@ flush UTLB

		mov	pc, r12



__arm6_mmu_cache_on:

		mov	r12, lr

		bl	__setup_mmu
@@ -636,6 +650,12 @@ proc_types: 
		b	__armv4_mmu_cache_off

		b	__armv5tej_mmu_cache_flush



		.word	0x66015261		@ FA526

		.word	0xff01fff1

		b	__fa526_cache_on

		b	__armv4_mmu_cache_off

		b	__fa526_cache_flush



		@ These match on the architecture ID



		.word	0x00020000		@ ARMv4T
@@ -775,6 +795,12 @@ __armv4_mpu_cache_flush: 
		mcr	p15, 0, ip, c7, c10, 4	@ drain WB

		mov	pc, lr

		

__fa526_cache_flush:

		mov	r1, #0

		mcr	p15, 0, r1, c7, c14, 0	@ clean and invalidate D cache

		mcr	p15, 0, r1, c7, c5, 0	@ flush I cache

		mcr	p15, 0, r1, c7, c10, 4	@ drain WB

		mov	pc, lr



__armv6_mmu_cache_flush:

		mov	r1, #0

arch/arm/include/asm/cacheflush.h

+8 −0
Original line number Diff line number Diff line
@@ -46,6 +46,14 @@ 
# define MULTI_CACHE 1

#endif



#if defined(CONFIG_CPU_FA526)

# ifdef _CACHE

#  define MULTI_CACHE 1

# else

#  define _CACHE fa

# endif

#endif



#if defined(CONFIG_CPU_ARM926T)

# ifdef _CACHE

#  define MULTI_CACHE 1

arch/arm/include/asm/page.h

+8 −0
Original line number Diff line number Diff line
@@ -76,6 +76,14 @@ 
# endif

#endif



#ifdef CONFIG_CPU_COPY_FA

# ifdef _USER

#  define MULTI_USER 1

# else

#  define _USER fa

# endif

#endif



#ifdef CONFIG_CPU_SA1100

# ifdef _USER

#  define MULTI_USER 1

arch/arm/include/asm/proc-fns.h

+8 −0
Original line number Diff line number Diff line
@@ -89,6 +89,14 @@ 
#   define CPU_NAME cpu_arm922

#  endif

# endif

# ifdef CONFIG_CPU_FA526

#  ifdef CPU_NAME

#   undef  MULTI_CPU

#   define MULTI_CPU

#  else

#   define CPU_NAME cpu_fa526

#  endif

# endif

# ifdef CONFIG_CPU_ARM925T

#  ifdef CPU_NAME

#   undef  MULTI_CPU