Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 287ccf10 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: msm: clock-gcc-8996: Control gcc_aggre0_noc_mpu_cfg_ahb_clk from HLOS



Add support in the clock driver to model and control
this clock on msm8996. This clock is used by the bus
driver to set the QoS registers for the Aggre0 masters.

Change-Id: I26f94d4ea410d4c1c099c9ede0313b8704ce3d68
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent f81d0b1f
Loading
Loading
Loading
Loading
+13 −0
Original line number Diff line number Diff line
@@ -3143,6 +3143,17 @@ static struct branch_clk gcc_dcc_ahb_clk = {
	},
};

static struct branch_clk gcc_aggre0_noc_mpu_cfg_ahb_clk = {
	.cbcr_reg = GCC_AGGRE0_NOC_MPU_CFG_AHB_CBCR,
	.has_sibling = 1,
	.base = &virt_base,
	.c = {
		.dbg_name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
		.ops = &clk_ops_branch,
		CLK_INIT(gcc_aggre0_noc_mpu_cfg_ahb_clk.c),
	},
};

static struct mux_clk gcc_debug_mux;
static struct mux_clk gcc_debug_mux_v2;
static struct clk_ops clk_ops_debug_mux;
@@ -3290,6 +3301,7 @@ static struct mux_clk gcc_debug_mux = {
		{ &gcc_aggre2_ufs_axi_clk.c, 0x0126 },
		{ &gcc_aggre2_usb3_axi_clk.c, 0x0127 },
		{ &gcc_dcc_ahb_clk.c, 0x012b },
		{ &gcc_aggre0_noc_mpu_cfg_ahb_clk.c, 0x012c},
		{ &ipa_clk.c, 0x12f },
	),
	.c = {
@@ -3583,6 +3595,7 @@ static struct clk_lookup msm_clocks_gcc_8996[] = {
	CLK_LIST(gcc_mmss_bimc_gfx_clk),
	CLK_LIST(gcc_bimc_gfx_clk),
	CLK_LIST(gcc_dcc_ahb_clk),
	CLK_LIST(gcc_aggre0_noc_mpu_cfg_ahb_clk),
};

static struct clk_lookup msm_clocks_gcc_8996_v2[] = {
+1 −0
Original line number Diff line number Diff line
@@ -289,6 +289,7 @@
#define clk_gpll0_out_msscc		0x7d794829
#define clk_gcc_debug_mux_v2		0xf7e749f0
#define clk_gcc_dcc_ahb_clk		0xfa14a88c
#define clk_gcc_aggre0_noc_mpu_cfg_ahb_clk	0x5c1bb8e2

/* clock_mmss controlled clocks */
#define clk_mmsscc_xo			0x05e63704
+1 −0
Original line number Diff line number Diff line
@@ -495,3 +495,4 @@
#define GCC_MSS_SNOC_AXI_CBCR					(0x8A024)
#define GCC_MSS_MNOC_BIMC_AXI_CBCR				(0x8A004)
#define GCC_DCC_AHB_CBCR					(0x84004)
#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CBCR				(0x85000)