m32r: Convert genirq namespace (27e5c5a9) · Commits · e / devices / android_kernel_xiaomi_markw

arch/m32r/platforms/m32104ut/setup.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -76,7 +76,7 @@ void __init init_IRQ(void)

		#if defined(CONFIG_SMC91X)
		/* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
		set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
		handle_level_irq);
		/* "H" level sense */
		cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN \| M32R_ICUCR_ISMOD11;
		@@ -84,20 +84,20 @@ void __init init_IRQ(void)
		#endif /* CONFIG_SMC91X */

		/* MFT2 : system timer */
		set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
		disable_m32104ut_irq(M32R_IRQ_MFT2);

		#ifdef CONFIG_SERIAL_M32R_SIO
		/* SIO0_R : uart receive data */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
		disable_m32104ut_irq(M32R_IRQ_SIO0_R);

		/* SIO0_S : uart send data */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
		disable_m32104ut_irq(M32R_IRQ_SIO0_S);

arch/m32r/platforms/m32700ut/setup.c

+14 −14

Original line number	Diff line number	Diff line
		@@ -259,76 +259,76 @@ void __init init_IRQ(void)
		{
		#if defined(CONFIG_SMC91X)
		/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
		set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN,
		irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN,
		&m32700ut_lanpld_irq_type, handle_level_irq);
		lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* "H" edge sense */
		disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
		#endif /* CONFIG_SMC91X */

		/* MFT2 : system timer */
		set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
		disable_m32700ut_irq(M32R_IRQ_MFT2);

		/* SIO0 : receive */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_R].icucr = 0;
		disable_m32700ut_irq(M32R_IRQ_SIO0_R);

		/* SIO0 : send */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_S].icucr = 0;
		disable_m32700ut_irq(M32R_IRQ_SIO0_S);

		/* SIO1 : receive */
		set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO1_R].icucr = 0;
		disable_m32700ut_irq(M32R_IRQ_SIO1_R);

		/* SIO1 : send */
		set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO1_S].icucr = 0;
		disable_m32700ut_irq(M32R_IRQ_SIO1_S);

		/* DMA1 : */
		set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_DMA1].icucr = 0;
		disable_m32700ut_irq(M32R_IRQ_DMA1);

		#ifdef CONFIG_SERIAL_M32R_PLDSIO
		/* INT#1: SIO0 Receive on PLD */
		set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
		handle_level_irq);
		pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
		disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);

		/* INT#1: SIO0 Send on PLD */
		set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
		handle_level_irq);
		pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
		disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
		#endif /* CONFIG_SERIAL_M32R_PLDSIO */

		/* INT#1: CFC IREQ on PLD */
		set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
		handle_level_irq);
		pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* 'L' level sense */
		disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);

		/* INT#1: CFC Insert on PLD */
		set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
		handle_level_irq);
		pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
		disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);

		/* INT#1: CFC Eject on PLD */
		set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
		handle_level_irq);
		pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
		disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
		@@ -349,7 +349,7 @@ void __init init_IRQ(void)

		#if defined(CONFIG_USB)
		outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
		set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
		irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
		&m32700ut_lcdpld_irq_type, handle_level_irq);

		lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* "L" level sense */
		@@ -366,7 +366,7 @@ void __init init_IRQ(void)
		/*
		* INT3# is used for AR
		*/
		set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
		disable_m32700ut_irq(M32R_IRQ_INT3);

arch/m32r/platforms/mappi/setup.c

+8 −8

Original line number	Diff line number	Diff line
		@@ -75,39 +75,39 @@ void __init init_IRQ(void)

		#ifdef CONFIG_NE2000
		/* INT0 : LAN controller (RTL8019AS) */
		set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD11;
		disable_mappi_irq(M32R_IRQ_INT0);
		#endif /* CONFIG_M32R_NE2000 */

		/* MFT2 : system timer */
		set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
		disable_mappi_irq(M32R_IRQ_MFT2);

		#ifdef CONFIG_SERIAL_M32R_SIO
		/* SIO0_R : uart receive data */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_R].icucr = 0;
		disable_mappi_irq(M32R_IRQ_SIO0_R);

		/* SIO0_S : uart send data */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_S].icucr = 0;
		disable_mappi_irq(M32R_IRQ_SIO0_S);

		/* SIO1_R : uart receive data */
		set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO1_R].icucr = 0;
		disable_mappi_irq(M32R_IRQ_SIO1_R);

		/* SIO1_S : uart send data */
		set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO1_S].icucr = 0;
		disable_mappi_irq(M32R_IRQ_SIO1_S);
		@@ -115,13 +115,13 @@ void __init init_IRQ(void)

		#if defined(CONFIG_M32R_PCC)
		/* INT1 : pccard0 interrupt */
		set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN \| M32R_ICUCR_ISMOD00;
		disable_mappi_irq(M32R_IRQ_INT1);

		/* INT2 : pccard1 interrupt */
		set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN \| M32R_ICUCR_ISMOD00;
		disable_mappi_irq(M32R_IRQ_INT2);

arch/m32r/platforms/mappi2/setup.c

+10 −10

Original line number	Diff line number	Diff line
		@@ -76,38 +76,38 @@ void __init init_IRQ(void)
		{
		#if defined(CONFIG_SMC91X)
		/* INT0 : LAN controller (SMC91111) */
		set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
		disable_mappi2_irq(M32R_IRQ_INT0);
		#endif /* CONFIG_SMC91X */

		/* MFT2 : system timer */
		set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
		disable_mappi2_irq(M32R_IRQ_MFT2);

		#ifdef CONFIG_SERIAL_M32R_SIO
		/* SIO0_R : uart receive data */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_R].icucr = 0;
		disable_mappi2_irq(M32R_IRQ_SIO0_R);

		/* SIO0_S : uart send data */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_S].icucr = 0;
		disable_mappi2_irq(M32R_IRQ_SIO0_S);
		/* SIO1_R : uart receive data */
		set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO1_R].icucr = 0;
		disable_mappi2_irq(M32R_IRQ_SIO1_R);

		/* SIO1_S : uart send data */
		set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO1_S].icucr = 0;
		disable_mappi2_irq(M32R_IRQ_SIO1_S);
		@@ -115,27 +115,27 @@ void __init init_IRQ(void)

		#if defined(CONFIG_USB)
		/* INT1 : USB Host controller interrupt */
		set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
		disable_mappi2_irq(M32R_IRQ_INT1);
		#endif /* CONFIG_USB */

		/* ICUCR40: CFC IREQ */
		set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
		handle_level_irq);
		icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD01;
		disable_mappi2_irq(PLD_IRQ_CFIREQ);

		#if defined(CONFIG_M32R_CFC)
		/* ICUCR41: CFC Insert */
		set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
		handle_level_irq);
		icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD00;
		disable_mappi2_irq(PLD_IRQ_CFC_INSERT);

		/* ICUCR42: CFC Eject */
		set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
		handle_level_irq);
		icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
		disable_mappi2_irq(PLD_IRQ_CFC_EJECT);

arch/m32r/platforms/mappi3/setup.c

+10 −10

Original line number	Diff line number	Diff line
		@@ -75,38 +75,38 @@ void __init init_IRQ(void)
		{
		#if defined(CONFIG_SMC91X)
		/* INT0 : LAN controller (SMC91111) */
		set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
		disable_mappi3_irq(M32R_IRQ_INT0);
		#endif /* CONFIG_SMC91X */

		/* MFT2 : system timer */
		set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
		disable_mappi3_irq(M32R_IRQ_MFT2);

		#ifdef CONFIG_SERIAL_M32R_SIO
		/* SIO0_R : uart receive data */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_R].icucr = 0;
		disable_mappi3_irq(M32R_IRQ_SIO0_R);

		/* SIO0_S : uart send data */
		set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO0_S].icucr = 0;
		disable_mappi3_irq(M32R_IRQ_SIO0_S);
		/* SIO1_R : uart receive data */
		set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO1_R].icucr = 0;
		disable_mappi3_irq(M32R_IRQ_SIO1_R);

		/* SIO1_S : uart send data */
		set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_SIO1_S].icucr = 0;
		disable_mappi3_irq(M32R_IRQ_SIO1_S);
		@@ -114,21 +114,21 @@ void __init init_IRQ(void)

		#if defined(CONFIG_USB)
		/* INT1 : USB Host controller interrupt */
		set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
		irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
		handle_level_irq);
		icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
		disable_mappi3_irq(M32R_IRQ_INT1);
		#endif /* CONFIG_USB */

		/* CFC IREQ */
		set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
		handle_level_irq);
		icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD01;
		disable_mappi3_irq(PLD_IRQ_CFIREQ);

		#if defined(CONFIG_M32R_CFC)
		/* ICUCR41: CFC Insert & eject */
		set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
		handle_level_irq);
		icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD00;
		disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
		@@ -136,7 +136,7 @@ void __init init_IRQ(void)
		#endif /* CONFIG_M32R_CFC */

		/* IDE IREQ */
		set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
		irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
		handle_level_irq);
		icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
		disable_mappi3_irq(PLD_IRQ_IDEIREQ);