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Commit 279ce12c authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add PIL support for msmthorium"

parents 1a81505e ae5ce4e3

arch/arm/boot/dts/qcom/msmthorium-smp2p.dtsi

+69 −0
Original line number Diff line number Diff line
@@ -157,4 +157,73 @@ 
		compatible = "qcom,smp2pgpio_test_smp2p_2_out";

		gpios = <&smp2pgpio_smp2p_2_out 0 0>;

	};



	/* ssr - inbound entry from mss. */

	smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in {

		compatible = "qcom,smp2pgpio";

		qcom,entry-name = "slave-kernel";

		qcom,remote-pid = <1>;

		qcom,is-inbound;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};



	/* ssr - outbound entry to mss */

	smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out {

		compatible = "qcom,smp2pgpio";

		qcom,entry-name = "master-kernel";

		qcom,remote-pid = <1>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};



	/* ssr - inbound entry from lpass. */

	smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in {

		compatible = "qcom,smp2pgpio";

		qcom,entry-name = "slave-kernel";

		qcom,remote-pid = <2>;

		qcom,is-inbound;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};



	/* ssr - outbound entry to lpass */

	smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out {

		compatible = "qcom,smp2pgpio";

		qcom,entry-name = "master-kernel";

		qcom,remote-pid = <2>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};



	/* ssr - inbound entry from wcnss. */

	smp2pgpio_ssr_smp2p_4_in: qcom,smp2pgpio-ssr-smp2p-4-in {

		compatible = "qcom,smp2pgpio";

		qcom,entry-name = "slave-kernel";

		qcom,remote-pid = <4>;

		qcom,is-inbound;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};



	/* ssr - outbound entry to wcnss */

	smp2pgpio_ssr_smp2p_4_out: qcom,smp2pgpio-ssr-smp2p-4-out {

		compatible = "qcom,smp2pgpio";

		qcom,entry-name = "master-kernel";

		qcom,remote-pid = <4>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};

};

arch/arm/boot/dts/qcom/msmthorium.dtsi

+162 −0
Original line number Diff line number Diff line
@@ -812,6 +812,168 @@ 
		qcom,not-wakeup;

		status = "disabled";

	};



	qcom,mss@4080000 {

		compatible = "qcom,pil-q6v55-mss";

		reg = <0x04080000 0x100>,

		      <0x0194f000 0x010>,

		      <0x01950000 0x008>,

		      <0x01951000 0x008>,

		      <0x04020000 0x040>,

		      <0x01871000 0x004>;

		reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc",

				 "rmb_base", "restart_reg";



		interrupts = <0 24 1>;

		vdd_mss-supply = <&pmthorium_s1>;

		vdd_cx-supply = <&pmthorium_s2_level>;

		vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;

		vdd_mx-supply = <&pmthorium_l3_level_ao>;

		vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;

		vdd_pll-supply = <&pmthorium_l7>;

		qcom,vdd_pll = <1800000>;



		clocks = <&clock_gcc clk_xo_pil_mss_clk>,

			 <&clock_gcc clk_gcc_mss_cfg_ahb_clk>,

			 <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,

			 <&clock_gcc clk_gcc_boot_rom_ahb_clk>;

		clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";

		qcom,proxy-clock-names = "xo";

		qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";



		qcom,firmware-name = "modem";

		qcom,pil-self-auth;

		qcom,sysmon-id = <0>;

		qcom,ssctl-instance-id = <0x12>;

		qcom,qdsp6v56-1-8-inrush-current;



		/* GPIO inputs from mss */

		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;

		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;

		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;

		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;

		qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;



		/* GPIO output to mss */

		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;

		memory-region = <&modem_mem>;

	};



	qcom,lpass@c200000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0xc200000 0x00100>;

		interrupts = <0 293 1>;



		vdd_cx-supply = <&pmthorium_s2_level>;

		qcom,proxy-reg-names = "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;



		clocks = <&clock_gcc clk_xo_pil_lpass_clk>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>,

			 <&clock_gcc clk_crypto_clk_src>;

		clock-names = "xo", "scm_core_clk", "scm_iface_clk",

				"scm_bus_clk", "scm_core_clk_src";

		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",

				 "scm_bus_clk", "scm_core_clk_src";

		qcom,scm_core_clk_src-freq = <80000000>;



		qcom,pas-id = <1>;

		qcom,proxy-timeout-ms = <10000>;

		qcom,smem-id = <423>;

		qcom,sysmon-id = <1>;

		qcom,ssctl-instance-id = <0x14>;

		qcom,firmware-name = "adsp";



		/* GPIO inputs from lpass */

		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;

		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;

		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;

		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;



		/* GPIO output to lpass */

		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;



		memory-region = <&reloc_mem>;

	};



	qcom,pronto@a21b000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x0a21b000 0x3000>;

		interrupts = <0 149 1>;



		vdd_pronto_pll-supply = <&pmthorium_l7>;

		proxy-reg-names = "vdd_pronto_pll";

		vdd_pronto_pll-uV-uA = <1800000 18000>;

		clocks = <&clock_gcc clk_xo_pil_pronto_clk>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>,

			 <&clock_gcc clk_crypto_clk_src>;



		clock-names = "xo", "scm_core_clk", "scm_iface_clk",

				"scm_bus_clk", "scm_core_clk_src";

		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",

				 "scm_bus_clk", "scm_core_clk_src";

		qcom,scm_core_clk_src = <80000000>;



		qcom,pas-id = <6>;

		qcom,proxy-timeout-ms = <10000>;

		qcom,smem-id = <422>;

		qcom,sysmon-id = <6>;

		qcom,ssctl-instance-id = <0x13>;

		qcom,firmware-name = "wcnss";



		/* GPIO inputs from wcnss */

		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;

		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>;

		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>;

		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_4_in 3 0>;



		/* GPIO output to wcnss */

		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;

		memory-region = <&reloc_mem>;

	};



	qcom,venus@1de0000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x1de0000 0x4000>;



		vdd-supply = <&gdsc_venus>;

		qcom,proxy-reg-names = "vdd";



		clocks = <&clock_gcc clk_gcc_venus0_vcodec0_clk>,

			 <&clock_gcc clk_gcc_venus0_ahb_clk>,

			 <&clock_gcc clk_gcc_venus0_axi_clk>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>,

			 <&clock_gcc clk_crypto_clk_src>;



		clock-names = "core_clk", "iface_clk", "bus_clk",

				"scm_core_clk", "scm_iface_clk",

				"scm_bus_clk", "scm_core_clk_src";



		qcom,proxy-clock-names = "core_clk", "iface_clk",

					 "bus_clk", "scm_core_clk",

					 "scm_iface_clk", "scm_bus_clk",

					 "scm_core_clk_src";

		qcom,scm_core_clk_src-freq = <80000000>;



		qcom,msm-bus,name = "pil-venus";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<63 512 0 0>,

				<63 512 0 304000>;



		qcom,pas-id = <9>;

		qcom,proxy-timeout-ms = <100>;

		qcom,firmware-name = "venus";

		memory-region = <&venus_mem>;

	};



};



#include "msm-pmthorium-rpm-regulator.dtsi"