Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2729a0fa authored by CQ Tang's avatar CQ Tang Committed by Sasha Levin
Browse files

iommu/vt-d: Fix 64-bit accesses to 32-bit DMAR_GSTS_REG 



[ Upstream commit fda3bec12d0979aae3f02ee645913d66fbc8a26e ]

This is a 32-bit register. Apparently harmless on real hardware, but
causing justified warnings in simulation.

Signed-off-by: default avatarCQ Tang <cq.tang@intel.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent 17b6dde0

drivers/iommu/dmar.c

+1 −1
Original line number Diff line number Diff line
@@ -1272,7 +1272,7 @@ void dmar_disable_qi(struct intel_iommu *iommu) 


	raw_spin_lock_irqsave(&iommu->register_lock, flags);



	sts =  dmar_readq(iommu->reg + DMAR_GSTS_REG);

	sts =  readl(iommu->reg + DMAR_GSTS_REG);

	if (!(sts & DMA_GSTS_QIES))

		goto end;

drivers/iommu/intel_irq_remapping.c

+1 −1
Original line number Diff line number Diff line
@@ -531,7 +531,7 @@ static void iommu_disable_irq_remapping(struct intel_iommu *iommu) 


	raw_spin_lock_irqsave(&iommu->register_lock, flags);



	sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);

	sts = readl(iommu->reg + DMAR_GSTS_REG);

	if (!(sts & DMA_GSTS_IRES))

		goto end;