drm/radeon: switch to a finer grained reset for cayman/TN (271d6fed) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/gpu/drm/radeon/ni.c

+70 −39

Original line number	Original line	Diff line number	Diff line
	@@ -1306,15 +1306,13 @@ void cayman_dma_fini(struct radeon_device *rdev)
	radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);		radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
	}		}

	static int cayman_gpu_soft_reset(struct radeon_device *rdev)		static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev)
	{		{
	struct evergreen_mc_save save;		u32 grbm_reset = 0;
	u32 grbm_reset = 0, tmp;

	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))		if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
	return 0;		return;

	dev_info(rdev->dev, "GPU softreset \n");
	dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",		dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
	RREG32(GRBM_STATUS));		RREG32(GRBM_STATUS));
	dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",		dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
	@@ -1331,41 +1329,10 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
	RREG32(CP_BUSY_STAT));		RREG32(CP_BUSY_STAT));
	dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",		dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
	RREG32(CP_STAT));		RREG32(CP_STAT));
	dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
	RREG32(DMA_STATUS_REG));
	dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
	RREG32(0x14F8));
	dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
	RREG32(0x14D8));
	dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
	RREG32(0x14FC));
	dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
	RREG32(0x14DC));

	evergreen_mc_stop(rdev, &save);
	if (evergreen_mc_wait_for_idle(rdev)) {
	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
	}

	/* Disable CP parsing/prefetching */		/* Disable CP parsing/prefetching */
	WREG32(CP_ME_CNTL, CP_ME_HALT \| CP_PFP_HALT);		WREG32(CP_ME_CNTL, CP_ME_HALT \| CP_PFP_HALT);

	/* dma0 */
	tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
	tmp &= ~DMA_RB_ENABLE;
	WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

	/* dma1 */
	tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
	tmp &= ~DMA_RB_ENABLE;
	WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

	/* Reset dma */
	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA \| SOFT_RESET_DMA1);
	RREG32(SRBM_SOFT_RESET);
	udelay(50);
	WREG32(SRBM_SOFT_RESET, 0);

	/* reset all the gfx blocks */		/* reset all the gfx blocks */
	grbm_reset = (SOFT_RESET_CP \|		grbm_reset = (SOFT_RESET_CP \|
	SOFT_RESET_CB \|		SOFT_RESET_CB \|
	@@ -1387,8 +1354,6 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
	udelay(50);		udelay(50);
	WREG32(GRBM_SOFT_RESET, 0);		WREG32(GRBM_SOFT_RESET, 0);
	(void)RREG32(GRBM_SOFT_RESET);		(void)RREG32(GRBM_SOFT_RESET);
	/* Wait a little for things to settle down */
	udelay(50);

	dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",		dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
	RREG32(GRBM_STATUS));		RREG32(GRBM_STATUS));
	@@ -1406,15 +1371,81 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
	RREG32(CP_BUSY_STAT));		RREG32(CP_BUSY_STAT));
	dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",		dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
	RREG32(CP_STAT));		RREG32(CP_STAT));

			}

			static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev)
			{
			u32 tmp;

			if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
			return;

	dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",		dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
	RREG32(DMA_STATUS_REG));		RREG32(DMA_STATUS_REG));

			/* dma0 */
			tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
			tmp &= ~DMA_RB_ENABLE;
			WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

			/* dma1 */
			tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
			tmp &= ~DMA_RB_ENABLE;
			WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

			/* Reset dma */
			WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA \| SOFT_RESET_DMA1);
			RREG32(SRBM_SOFT_RESET);
			udelay(50);
			WREG32(SRBM_SOFT_RESET, 0);

			dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
			RREG32(DMA_STATUS_REG));

			}

			static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
			{
			struct evergreen_mc_save save;

			if (reset_mask == 0)
			return 0;

			dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

			dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
			RREG32(0x14F8));
			dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
			RREG32(0x14D8));
			dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
			RREG32(0x14FC));
			dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
			RREG32(0x14DC));

			evergreen_mc_stop(rdev, &save);
			if (evergreen_mc_wait_for_idle(rdev)) {
			dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
			}

			if (reset_mask & (RADEON_RESET_GFX \| RADEON_RESET_COMPUTE))
			cayman_gpu_soft_reset_gfx(rdev);

			if (reset_mask & RADEON_RESET_DMA)
			cayman_gpu_soft_reset_dma(rdev);

			/* Wait a little for things to settle down */
			udelay(50);

	evergreen_mc_resume(rdev, &save);		evergreen_mc_resume(rdev, &save);
	return 0;		return 0;
	}		}

	int cayman_asic_reset(struct radeon_device *rdev)		int cayman_asic_reset(struct radeon_device *rdev)
	{		{
	return cayman_gpu_soft_reset(rdev);		return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX \|
			RADEON_RESET_COMPUTE \|
			RADEON_RESET_DMA));
	}		}

	/**		/**