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Commit 26ec85b9 authored by Asutosh Das's avatar Asutosh Das
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mmc: core: support DDR52 bus-speed during eMMC clock scaling 



Add support for DDR52 bus-speed mode during clock scaling.
The reason for this change is DDR52 can be supported at SVS
mode.

Change-Id: I68e5fca57ae5cbc154f5dd7001df368900cb3f57
Signed-off-by: default avatarAsutosh Das <asutoshd@codeaurora.org>
parent abba9462
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