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Commit 25a34554 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-fixes-for-linus' of... 

Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, pvclock: Remove leftover scale_delta() function
  x86, apic: Remove double #include
  x86: Adjust section annotations in AMD Fam10 MMCONF enabling code
  x86, UV: Update node controller MMRs
  x86: Remove unnecessary casts of void ptr returning alloc function return values
  x86: Address gcc4.6 "set but not used" warnings in apic.h
  x86, mm: Fix section mismatch in tlb.c
parents 28397bab 1f523bf3

arch/x86/include/asm/apic.h

+5 −5
Original line number Diff line number Diff line
@@ -141,13 +141,13 @@ static inline void native_apic_msr_write(u32 reg, u32 v) 


static inline u32 native_apic_msr_read(u32 reg)

{

	u32 low, high;

	u64 msr;



	if (reg == APIC_DFR)

		return -1;



	rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);

	return low;

	rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);

	return (u32)msr;

}



static inline void native_x2apic_wait_icr_idle(void)
@@ -181,12 +181,12 @@ extern void enable_x2apic(void); 
extern void x2apic_icr_write(u32 low, u32 id);

static inline int x2apic_enabled(void)

{

	int msr, msr2;

	u64 msr;



	if (!cpu_has_x2apic)

		return 0;



	rdmsr(MSR_IA32_APICBASE, msr, msr2);

	rdmsrl(MSR_IA32_APICBASE, msr);

	if (msr & X2APIC_ENABLE)

		return 1;

	return 0;

arch/x86/include/asm/uv/uv_mmrs.h

+96 −93
Original line number Diff line number Diff line
@@ -805,6 +805,78 @@ union uvh_node_present_table_u { 
    } s;

};



/* ========================================================================= */

/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */

/* ========================================================================= */

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL



#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL



union uvh_rh_gam_alias210_overlay_config_0_mmr_u {

    unsigned long	v;

    struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {

	unsigned long	rsvd_0_23: 24;  /*    */

	unsigned long	base    :  8;  /* RW */

	unsigned long	rsvd_32_47: 16;  /*    */

	unsigned long	m_alias :  5;  /* RW */

	unsigned long	rsvd_53_62: 10;  /*    */

	unsigned long	enable  :  1;  /* RW */

    } s;

};



/* ========================================================================= */

/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */

/* ========================================================================= */

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL



#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL



union uvh_rh_gam_alias210_overlay_config_1_mmr_u {

    unsigned long	v;

    struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {

	unsigned long	rsvd_0_23: 24;  /*    */

	unsigned long	base    :  8;  /* RW */

	unsigned long	rsvd_32_47: 16;  /*    */

	unsigned long	m_alias :  5;  /* RW */

	unsigned long	rsvd_53_62: 10;  /*    */

	unsigned long	enable  :  1;  /* RW */

    } s;

};



/* ========================================================================= */

/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */

/* ========================================================================= */

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL



#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL



union uvh_rh_gam_alias210_overlay_config_2_mmr_u {

    unsigned long	v;

    struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {

	unsigned long	rsvd_0_23: 24;  /*    */

	unsigned long	base    :  8;  /* RW */

	unsigned long	rsvd_32_47: 16;  /*    */

	unsigned long	m_alias :  5;  /* RW */

	unsigned long	rsvd_53_62: 10;  /*    */

	unsigned long	enable  :  1;  /* RW */

    } s;

};



/* ========================================================================= */

/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */

/* ========================================================================= */
@@ -856,6 +928,29 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 
    } s;

};



/* ========================================================================= */

/*                          UVH_RH_GAM_CONFIG_MMR                            */

/* ========================================================================= */

#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL



#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0

#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL

#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6

#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL

#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12

#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL



union uvh_rh_gam_config_mmr_u {

    unsigned long	v;

    struct uvh_rh_gam_config_mmr_s {

	unsigned long	m_skt     :  6;  /* RW */

	unsigned long	n_skt     :  4;  /* RW */

	unsigned long	rsvd_10_11:  2;  /*    */

	unsigned long	mmiol_cfg :  1;  /* RW */

	unsigned long	rsvd_13_63: 51;  /*    */

    } s;

};



/* ========================================================================= */

/*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */

/* ========================================================================= */
@@ -987,97 +1082,5 @@ union uvh_rtc1_int_config_u { 
    } s;

};



/* ========================================================================= */

/*                          UVH_SI_ADDR_MAP_CONFIG                           */

/* ========================================================================= */

#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL



#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0

#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL

#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8

#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL



union uvh_si_addr_map_config_u {

    unsigned long	v;

    struct uvh_si_addr_map_config_s {

	unsigned long	m_skt :  6;  /* RW */

	unsigned long	rsvd_6_7:  2;  /*    */

	unsigned long	n_skt :  4;  /* RW */

	unsigned long	rsvd_12_63: 52;  /*    */

    } s;

};



/* ========================================================================= */

/*                       UVH_SI_ALIAS0_OVERLAY_CONFIG                        */

/* ========================================================================= */

#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL



#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24

#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL

#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48

#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL

#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63

#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL



union uvh_si_alias0_overlay_config_u {

    unsigned long	v;

    struct uvh_si_alias0_overlay_config_s {

	unsigned long	rsvd_0_23: 24;  /*    */

	unsigned long	base    :  8;  /* RW */

	unsigned long	rsvd_32_47: 16;  /*    */

	unsigned long	m_alias :  5;  /* RW */

	unsigned long	rsvd_53_62: 10;  /*    */

	unsigned long	enable  :  1;  /* RW */

    } s;

};



/* ========================================================================= */

/*                       UVH_SI_ALIAS1_OVERLAY_CONFIG                        */

/* ========================================================================= */

#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL



#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24

#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL

#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48

#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL

#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63

#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL



union uvh_si_alias1_overlay_config_u {

    unsigned long	v;

    struct uvh_si_alias1_overlay_config_s {

	unsigned long	rsvd_0_23: 24;  /*    */

	unsigned long	base    :  8;  /* RW */

	unsigned long	rsvd_32_47: 16;  /*    */

	unsigned long	m_alias :  5;  /* RW */

	unsigned long	rsvd_53_62: 10;  /*    */

	unsigned long	enable  :  1;  /* RW */

    } s;

};



/* ========================================================================= */

/*                       UVH_SI_ALIAS2_OVERLAY_CONFIG                        */

/* ========================================================================= */

#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL



#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24

#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL

#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48

#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL

#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63

#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL



union uvh_si_alias2_overlay_config_u {

    unsigned long	v;

    struct uvh_si_alias2_overlay_config_s {

	unsigned long	rsvd_0_23: 24;  /*    */

	unsigned long	base    :  8;  /* RW */

	unsigned long	rsvd_32_47: 16;  /*    */

	unsigned long	m_alias :  5;  /* RW */

	unsigned long	rsvd_53_62: 10;  /*    */

	unsigned long	enable  :  1;  /* RW */

    } s;

};





#endif /* _ASM_X86_UV_UV_MMRS_H */
 
#endif /* __ASM_UV_MMRS_X86_H__ */

arch/x86/kernel/apic/apic.c

+0 −1
Original line number Diff line number Diff line
@@ -52,7 +52,6 @@ 
#include <asm/mce.h>

#include <asm/kvm_para.h>

#include <asm/tsc.h>

#include <asm/atomic.h>



unsigned int num_processors;

arch/x86/kernel/apic/x2apic_uv_x.c

+6 −6
Original line number Diff line number Diff line
@@ -379,14 +379,14 @@ struct redir_addr { 
#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT



static __initdata struct redir_addr redir_addrs[] = {

	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},

	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},

	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},

	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},

	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},

	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},

};



static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)

{

	union uvh_si_alias0_overlay_config_u alias;

	union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;

	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;

	int i;
@@ -660,7 +660,7 @@ void uv_nmi_init(void) 


void __init uv_system_init(void)

{

	union uvh_si_addr_map_config_u m_n_config;

	union uvh_rh_gam_config_mmr_u  m_n_config;

	union uvh_node_id_u node_id;

	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;

	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
@@ -670,7 +670,7 @@ void __init uv_system_init(void) 


	map_low_mmrs();



	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);

	m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );

	m_val = m_n_config.s.m_skt;

	n_val = m_n_config.s.n_skt;

	mmr_base =

arch/x86/kernel/microcode_amd.c

+1 −1
Original line number Diff line number Diff line
@@ -212,7 +212,7 @@ static int install_equiv_cpu_table(const u8 *buf) 
		return 0;

	}



	equiv_cpu_table = (struct equiv_cpu_entry *) vmalloc(size);

	equiv_cpu_table = vmalloc(size);

	if (!equiv_cpu_table) {

		pr_err("failed to allocate equivalent CPU table\n");

		return 0;