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Commit 25724841 authored by Will Deacon's avatar Will Deacon
Browse files

iommu/arm-smmu: use relaxed accessors where possible 



Apart from fault handling and page table manipulation, we don't care
about memory ordering between SMMU control registers and normal,
cacheable memory, so use the _relaxed I/O accessors wherever possible.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 8a7f4312

drivers/iommu/arm-smmu.c

+3 −3
Original line number Diff line number Diff line
@@ -778,7 +778,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) 
#ifdef __BIG_ENDIAN

	reg |= SCTLR_E;

#endif

	writel(reg, cb_base + ARM_SMMU_CB_SCTLR);

	writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);

}



static int arm_smmu_init_domain_context(struct iommu_domain *domain,
@@ -1595,7 +1595,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) 


	/* Push the button */

	arm_smmu_tlb_sync(smmu);

	writel(scr0, gr0_base + ARM_SMMU_GR0_sCR0);

	writel_relaxed(scr0, gr0_base + ARM_SMMU_GR0_sCR0);

}



static int arm_smmu_id_size_to_bits(int size)
@@ -1928,7 +1928,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev) 
		free_irq(smmu->irqs[i], smmu);



	/* Turn the thing off */

	writel(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);

	writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);

	return 0;

}