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Commit 2547c0a5 authored by Carter Cooper's avatar Carter Cooper
Browse files

msm: kgsl: Use kernel defines to access 32bit values 



Rather than writing our own functions to grab the upper and
lower 32 bits of a 64 bit number, use what the kernel
already has for us.

Change-Id: I7a583ba9cc793208bcf96af093870e7e567a5130
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent f5d3db32

drivers/gpu/msm/adreno.c

+2 −2
Original line number Diff line number Diff line
@@ -155,10 +155,10 @@ void adreno_writereg64(struct adreno_device *adreno_dev, 


	if (adreno_checkreg_off(adreno_dev, lo))

		kgsl_regwrite(device, gpudev->reg_offsets->offsets[lo],

			((unsigned int)val));

				lower_32_bits(val));

	if (adreno_checkreg_off(adreno_dev, hi))

		kgsl_regwrite(device, gpudev->reg_offsets->offsets[hi],

			((uint64_t)(val) >> 32));

				upper_32_bits(val));

}



/**

drivers/gpu/msm/adreno.h

+0 −10
Original line number Diff line number Diff line
@@ -1358,16 +1358,6 @@ static inline bool adreno_is_preemption_enabled( 
	return test_bit(ADRENO_DEVICE_PREEMPTION, &adreno_dev->priv);

}



static inline uint _lo_32(uint64_t val)

{

	return (uint) (val & 0xFFFFFFFF);

}



static inline uint _hi_32(uint64_t val)

{

	return (uint) ((val >> 32) & 0xFFFFFFFF);

}



static inline bool adreno_soft_fault_detect(struct adreno_device *adreno_dev)

{

	return adreno_dev->fast_hang_detect &&

drivers/gpu/msm/adreno_a5xx.c

+10 −11
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ 


#include "adreno.h"

#include "a5xx_reg.h"

#include "adreno_a3xx.h"

#include "adreno_a5xx.h"

#include "adreno_cp_parser.h"

#include "adreno_trace.h"
@@ -125,9 +124,9 @@ static void a5xx_preemption_start(struct adreno_device *adreno_dev, 
	kgsl_sharedmem_writel(device, &rb->preemption_desc,

		PREEMPT_RECORD(wptr), rb->wptr);

	kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO,

		_lo_32(rb->preemption_desc.gpuaddr));

		lower_32_bits(rb->preemption_desc.gpuaddr));

	kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI,

		_hi_32(rb->preemption_desc.gpuaddr));

		upper_32_bits(rb->preemption_desc.gpuaddr));

	kgsl_sharedmem_readq(&rb->pagetable_desc, &ttbr0,

		offsetof(struct adreno_ringbuffer_pagetable_info, ttbr0));

	kgsl_sharedmem_readl(&rb->pagetable_desc, &contextidr,
@@ -289,9 +288,9 @@ static int a5xx_preemption_pre_ibsubmit( 
	 * a5xx_cp_preemption_record pointed by CONTEXT_SWITCH_SAVE_ADDR

	 */

	*cmds++ = cp_type4_packet(A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 1);

	*cmds++ = _lo_32(gpuaddr);

	*cmds++ = lower_32_bits(gpuaddr);

	*cmds++ = cp_type4_packet(A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI, 1);

	*cmds++ = _hi_32(gpuaddr);

	*cmds++ = upper_32_bits(gpuaddr);



	/* Turn CP protection ON */

	*cmds++ = cp_type7_packet(CP_SET_PROTECTED_MODE, 1);
@@ -1943,9 +1942,9 @@ static int _preemption_init( 
	 * a5xx_cp_preemption_record pointed by CONTEXT_SWITCH_SAVE_ADDR

	 */

	*cmds++ = cp_type4_packet(A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 1);

	*cmds++ = _lo_32(gpuaddr);

	*cmds++ = lower_32_bits(gpuaddr);

	*cmds++ = cp_type4_packet(A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI, 1);

	*cmds++ = _hi_32(gpuaddr);

	*cmds++ = upper_32_bits(gpuaddr);



	/* Turn CP protection ON */

	*cmds++ = cp_type7_packet(CP_SET_PROTECTED_MODE, 1);
@@ -2177,15 +2176,15 @@ static int a5xx_microcode_load(struct adreno_device *adreno_dev, 


	gpuaddr = adreno_dev->pm4.gpuaddr;

	kgsl_regwrite(device, A5XX_CP_PM4_INSTR_BASE_LO,

				(uint)gpuaddr);

				lower_32_bits(gpuaddr));

	kgsl_regwrite(device, A5XX_CP_PM4_INSTR_BASE_HI,

				((uint64_t)(gpuaddr) >> 32));

				upper_32_bits(gpuaddr));



	gpuaddr = adreno_dev->pfp.gpuaddr;

	kgsl_regwrite(device, A5XX_CP_PFP_INSTR_BASE_LO,

				(uint)gpuaddr);

				lower_32_bits(gpuaddr));

	kgsl_regwrite(device, A5XX_CP_PFP_INSTR_BASE_HI,

				((uint64_t)(gpuaddr) >> 32));

				upper_32_bits(gpuaddr));



	/*

	 * Resume call to write the zap shader base address into the

drivers/gpu/msm/adreno_a5xx_snapshot.c

+2 −2
Original line number Diff line number Diff line
@@ -766,9 +766,9 @@ size_t a5xx_snapshot_regs_crash_dumper(struct kgsl_device *device, u8 *buf, 
	*(script_ptr++) = 0x0;



	kgsl_regwrite(device, A5XX_CP_CRASH_SCRIPT_BASE_LO,

			_lo_32(adreno_dev->capturescript.gpuaddr));

			lower_32_bits(adreno_dev->capturescript.gpuaddr));

	kgsl_regwrite(device, A5XX_CP_CRASH_SCRIPT_BASE_HI,

			_hi_32(adreno_dev->capturescript.gpuaddr));

			upper_32_bits(adreno_dev->capturescript.gpuaddr));

	kgsl_regwrite(device, A5XX_CP_CRASH_DUMP_CNTL, 1);



	wait_time = jiffies + msecs_to_jiffies(CP_CRASH_DUMPER_TIMEOUT);

drivers/gpu/msm/adreno_iommu.c

+11 −11
Original line number Diff line number Diff line
@@ -459,8 +459,8 @@ static unsigned int _adreno_iommu_set_pt_v1(struct adreno_ringbuffer *rb, 
	cmds += _iommu_lock(adreno_dev, cmds);



	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TTBR0, 2);

	*cmds++ = _lo_32(ttbr0);

	*cmds++ = _hi_32(ttbr0);

	*cmds++ = lower_32_bits(ttbr0);

	*cmds++ = upper_32_bits(ttbr0);

	cmds += _cp_smmu_reg(adreno_dev, cmds,

			KGSL_IOMMU_CTX_CONTEXTIDR, 1);

	*cmds++ = contextidr;
@@ -498,8 +498,8 @@ static unsigned int _adreno_iommu_set_pt_v2_a3xx(struct kgsl_device *device, 
	cmds += _vbif_lock(adreno_dev, cmds);



	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TTBR0, 2);

	*cmds++ = _lo_32(ttbr0);

	*cmds++ = _hi_32(ttbr0);

	*cmds++ = lower_32_bits(ttbr0);

	*cmds++ = upper_32_bits(ttbr0);

	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_CONTEXTIDR, 1);

	*cmds++ = contextidr;
@@ -527,8 +527,8 @@ static unsigned int _adreno_iommu_set_pt_v2_a4xx(struct kgsl_device *device, 
	cmds += _vbif_lock(adreno_dev, cmds);



	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_TTBR0, 2);

	*cmds++ = _lo_32(ttbr0);

	*cmds++ = _hi_32(ttbr0);

	*cmds++ = lower_32_bits(ttbr0);

	*cmds++ = upper_32_bits(ttbr0);

	cmds += _cp_smmu_reg(adreno_dev, cmds, KGSL_IOMMU_CTX_CONTEXTIDR, 1);

	*cmds++ = contextidr;
@@ -557,15 +557,15 @@ static unsigned int _adreno_iommu_set_pt_v2_a5xx(struct kgsl_device *device, 


	/* CP switches the pagetable and flushes the Caches */

	*cmds++ = cp_packet(adreno_dev, CP_SMMU_TABLE_UPDATE, 3);

	*cmds++ = _lo_32(ttbr0);

	*cmds++ = _hi_32(ttbr0);

	*cmds++ = lower_32_bits(ttbr0);

	*cmds++ = upper_32_bits(ttbr0);

	*cmds++ = contextidr;



	*cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 4, 1);

	cmds += cp_gpuaddr(adreno_dev, cmds, (rb->pagetable_desc.gpuaddr +

		offsetof(struct adreno_ringbuffer_pagetable_info, ttbr0)));

	*cmds++ = _lo_32(ttbr0);

	*cmds++ = _hi_32(ttbr0);

	*cmds++ = lower_32_bits(ttbr0);

	*cmds++ = upper_32_bits(ttbr0);

	*cmds++ = contextidr;



	/* release all commands with wait_for_me */
@@ -650,7 +650,7 @@ unsigned int adreno_iommu_set_pt_ib(struct adreno_ringbuffer *rb, 
			(rb->pagetable_desc.gpuaddr +

			offsetof(struct adreno_ringbuffer_pagetable_info,

			ttbr0)));

	*cmds++ = _lo_32(iommu_pt->ttbr0);

	*cmds++ = lower_32_bits(iommu_pt->ttbr0);



	*cmds++ =  cp_mem_packet(adreno_dev, CP_MEM_WRITE, 2, 1);

	cmds += cp_gpuaddr(adreno_dev, cmds,