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Commit 24afa004 authored by Gidon Studinski's avatar Gidon Studinski
Browse files

msm: ipa3: add IPA 3.0 support 



Add support to IPA 3.0 version and remove IPA 2.x support

Change-Id: Iff4213c8229c5436b0391a41e78f1ac069b0e06c
Acked-by: default avatarAdy Abraham <adya@qti.qualcomm.com>
Signed-off-by: default avatarNadine Toledano <nadinet@codeaurora.org>
Signed-off-by: default avatarAmir Levy <alevy@codeaurora.org>
Signed-off-by: default avatarGidon Studinski <gidons@codeaurora.org>
parent 7017803e

drivers/platform/msm/ipa/ipa_rm_inactivity_timer.c

+1 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

drivers/platform/msm/ipa/ipa_v3/ipa.c

+125 −364
Original line number Diff line number Diff line
@@ -42,8 +42,6 @@ 
#define IPA_CNOC_CLK_RATE (75 * 1000 * 1000UL)

#define IPA_A5_MUX_HEADER_LENGTH (8)

#define IPA_ROUTING_RULE_BYTE_SIZE (4)

#define IPA_BAM_CNFG_BITS_VALv1_1 (0x7FFFE004)

#define IPA_BAM_CNFG_BITS_VALv2_0 (0xFFFFE004)

#define IPA_STATUS_CLEAR_OFST (0x3f28)

#define IPA_STATUS_CLEAR_SIZE (32)
@@ -185,12 +183,8 @@ static struct of_device_id ipa_plat_drv_match[] = { 
};

struct msm_bus_scale_pdata *bus_scale_table;



static struct clk *ipa_clk_src;

static struct clk *ipa_clk;

static struct clk *smmu_clk;

static struct clk *sys_noc_ipa_axi_clk;

static struct clk *ipa_cnoc_clk;

static struct clk *ipa_inactivity_clk;



struct ipa_context *ipa_ctx;

static struct device *master_dev;
@@ -1124,18 +1118,8 @@ static int ipa_setup_exception_path(void) 
	hdr->commit = 1;

	hdr_entry = &hdr->hdr[0];



	if (ipa_ctx->ipa_hw_type == IPA_HW_v1_1) {

		strlcpy(hdr_entry->name, IPA_A5_MUX_HDR_NAME,

				IPA_RESOURCE_NAME_MAX);

		/* set template for the A5_MUX hdr in header addition block */

		hdr_entry->hdr_len = IPA_A5_MUX_HEADER_LENGTH;

	} else if (ipa_ctx->ipa_hw_type >= IPA_HW_v2_0) {

		strlcpy(hdr_entry->name, IPA_LAN_RX_HDR_NAME,

				IPA_RESOURCE_NAME_MAX);

	strlcpy(hdr_entry->name, IPA_LAN_RX_HDR_NAME, IPA_RESOURCE_NAME_MAX);

	hdr_entry->hdr_len = IPA_LAN_RX_HEADER_LENGTH;

	} else {

		WARN_ON(1);

	}



	if (ipa_add_hdr(hdr)) {

		IPAERR("fail to add exception hdr\n");
@@ -1329,7 +1313,7 @@ static int ipa_q6_avoid_holb(void) 
				IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_TIMER_BMSK);



			ipa_write_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v2_0(ep_idx),

			IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v3_0(ep_idx),

				reg_val);



			reg_val = 0;
@@ -1338,7 +1322,7 @@ static int ipa_q6_avoid_holb(void) 
				IPA_ENDP_INIT_HOL_BLOCK_EN_N_EN_BMSK);



			ipa_write_reg(ipa_ctx->mmio,

				IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v2_0(ep_idx),

				IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v3_0(ep_idx),

				reg_val);



			ipa_cfg_ep_ctrl(ep_idx, &avoid_holb);
@@ -1493,7 +1477,7 @@ static void ipa_q6_disable_agg_reg(struct ipa_register_write *reg_write, 
{

	reg_write->skip_pipeline_clear = 0;



	reg_write->offset = IPA_ENDP_INIT_AGGR_N_OFST_v2_0(ep_idx);

	reg_write->offset = IPA_ENDP_INIT_AGGR_N_OFST_v3_0(ep_idx);

	reg_write->value =

		(1 & IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK) <<

		IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT;
@@ -1665,118 +1649,25 @@ int ipa_q6_cleanup(void) 
	return 0;

}



int _ipa_init_sram_v2(void)

{

	u32 *ipa_sram_mmio;

	unsigned long phys_addr;

	struct ipa_hw_imm_cmd_dma_shared_mem cmd = {0};

	struct ipa_desc desc = {0};

	struct ipa_mem_buffer mem;

	int rc = 0;



	phys_addr = ipa_ctx->ipa_wrapper_base +

		ipa_ctx->ctrl->ipa_reg_base_ofst +

		IPA_SRAM_DIRECT_ACCESS_N_OFST_v2_0(

			ipa_ctx->smem_restricted_bytes / 4);



	ipa_sram_mmio = ioremap(phys_addr,

			ipa_ctx->smem_sz - ipa_ctx->smem_restricted_bytes);

	if (!ipa_sram_mmio) {

		IPAERR("fail to ioremap IPA SRAM\n");

		return -ENOMEM;

	}



#define IPA_SRAM_SET(ofst, val) (ipa_sram_mmio[(ofst - 4) / 4] = val)



	IPA_SRAM_SET(IPA_MEM_PART(v6_flt_ofst) - 4, IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v6_flt_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v4_rt_ofst) - 4, IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v4_rt_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v6_rt_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(modem_hdr_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(modem_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(apps_v4_flt_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(uc_info_ofst), IPA_MEM_CANARY_VAL);



	iounmap(ipa_sram_mmio);



	mem.size = IPA_STATUS_CLEAR_SIZE;

	mem.base = dma_alloc_coherent(ipa_ctx->pdev, mem.size, &mem.phys_base,

			GFP_KERNEL);

	if (!mem.base) {

		IPAERR("fail to alloc DMA buff of size %d\n", mem.size);

		return -ENOMEM;

	}

	memset(mem.base, 0, mem.size);



	cmd.size = mem.size;

	cmd.system_addr = mem.phys_base;

	cmd.local_addr = IPA_STATUS_CLEAR_OFST;

	desc.opcode = IPA_DMA_SHARED_MEM;

	desc.pyld = &cmd;

	desc.len = sizeof(struct ipa_hw_imm_cmd_dma_shared_mem);

	desc.type = IPA_IMM_CMD_DESC;



	if (ipa_send_cmd(1, &desc)) {

		IPAERR("fail to send immediate command\n");

		rc = -EFAULT;

	}



	dma_free_coherent(ipa_ctx->pdev, mem.size, mem.base, mem.phys_base);

	return rc;

}



int _ipa_init_sram_v2_5(void)

{

	u32 *ipa_sram_mmio;

	unsigned long phys_addr;



	phys_addr = ipa_ctx->ipa_wrapper_base +

			ipa_ctx->ctrl->ipa_reg_base_ofst +

			IPA_SRAM_SW_FIRST_v2_5;



	ipa_sram_mmio = ioremap(phys_addr,

		ipa_ctx->smem_sz - ipa_ctx->smem_restricted_bytes);

	if (!ipa_sram_mmio) {

		IPAERR("fail to ioremap IPA SRAM\n");

		return -ENOMEM;

	}



#define IPA_SRAM_SET(ofst, val) (ipa_sram_mmio[(ofst - 4) / 4] = val)



	IPA_SRAM_SET(IPA_MEM_PART(v4_flt_ofst) - 4, IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v4_flt_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v6_flt_ofst) - 4, IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v6_flt_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v4_rt_ofst) - 4, IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v4_rt_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(v6_rt_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(modem_hdr_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(modem_hdr_proc_ctx_ofst) - 4,

							IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(modem_hdr_proc_ctx_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(modem_ofst), IPA_MEM_CANARY_VAL);

	IPA_SRAM_SET(IPA_MEM_PART(end_ofst), IPA_MEM_CANARY_VAL);



	iounmap(ipa_sram_mmio);



	return 0;

}



static inline void ipa_sram_set_canary(u32 *sram_mmio, int offset)

{

	/* Set 4 bytes of CANARY before the offset */

	sram_mmio[(offset - 4) / 4] = IPA_MEM_CANARY_VAL;

}



int _ipa_init_sram_v2_6L(void)

/**

 * _ipa_init_sram_v3_0() - Initialize IPA local SRAM.

 *

 * Return codes: 0 for success, negative value for failure

 */

int _ipa_init_sram_v3_0(void)

{

	u32 *ipa_sram_mmio;

	unsigned long phys_addr;



	phys_addr = ipa_ctx->ipa_wrapper_base +

		ipa_ctx->ctrl->ipa_reg_base_ofst +

		IPA_SRAM_SW_FIRST_v2_5;

		IPA_SRAM_SW_FIRST_v3_0;



	ipa_sram_mmio = ioremap(phys_addr,

		ipa_ctx->smem_sz - ipa_ctx->smem_restricted_bytes);
@@ -1795,9 +1686,9 @@ int _ipa_init_sram_v2_6L(void) 
	ipa_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_rt_ofst));

	ipa_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(modem_hdr_ofst));

	ipa_sram_set_canary(ipa_sram_mmio,

			    IPA_MEM_PART(modem_comp_decomp_ofst) - 4);

		IPA_MEM_PART(modem_hdr_proc_ctx_ofst) - 4);

	ipa_sram_set_canary(ipa_sram_mmio,

			    IPA_MEM_PART(modem_comp_decomp_ofst));

		IPA_MEM_PART(modem_hdr_proc_ctx_ofst));

	ipa_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(modem_ofst));

	ipa_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(end_ofst));
@@ -1806,43 +1697,12 @@ int _ipa_init_sram_v2_6L(void) 
	return 0;

}



int _ipa_init_hdr_v2(void)

{

	struct ipa_desc desc = { 0 };

	struct ipa_mem_buffer mem;

	struct ipa_hdr_init_local cmd;

	int rc = 0;



	mem.size = IPA_MEM_PART(modem_hdr_size) + IPA_MEM_PART(apps_hdr_size);

	mem.base = dma_alloc_coherent(ipa_ctx->pdev, mem.size, &mem.phys_base,

			GFP_KERNEL);

	if (!mem.base) {

		IPAERR("fail to alloc DMA buff of size %d\n", mem.size);

		return -ENOMEM;

	}

	memset(mem.base, 0, mem.size);



	cmd.hdr_table_src_addr = mem.phys_base;

	cmd.size_hdr_table = mem.size;

	cmd.hdr_table_dst_addr = ipa_ctx->smem_restricted_bytes +

		IPA_MEM_PART(modem_hdr_ofst);



	desc.opcode = IPA_HDR_INIT_LOCAL;

	desc.pyld = &cmd;

	desc.len = sizeof(struct ipa_hdr_init_local);

	desc.type = IPA_IMM_CMD_DESC;

	IPA_DUMP_BUFF(mem.base, mem.phys_base, mem.size);



	if (ipa_send_cmd(1, &desc)) {

		IPAERR("fail to send immediate command\n");

		rc = -EFAULT;

	}



	dma_free_coherent(ipa_ctx->pdev, mem.size, mem.base, mem.phys_base);

	return rc;

}



int _ipa_init_hdr_v2_5(void)

/**

 * _ipa_init_hdr_v3_0() - Initialize IPA header block.

 *

 * Return codes: 0 for success, negative value for failure

 */

int _ipa_init_hdr_v3_0(void)

{

	struct ipa_desc desc = { 0 };

	struct ipa_mem_buffer mem;
@@ -1918,13 +1778,12 @@ int _ipa_init_hdr_v2_5(void) 
	return 0;

}



int _ipa_init_hdr_v2_6L(void)

{

	/* Same implementation as IPAv2 */

	return _ipa_init_hdr_v2();

}



int _ipa_init_rt4_v2(void)

/**

 * _ipa_init_rt4_v3() - Initialize IPA routing block for IPv4.

 *

 * Return codes: 0 for success, negative value for failure

 */

int _ipa_init_rt4_v3(void)

{

	struct ipa_desc desc = { 0 };

	struct ipa_mem_buffer mem;
@@ -1975,7 +1834,12 @@ int _ipa_init_rt4_v2(void) 
	return rc;

}



int _ipa_init_rt6_v2(void)

/**

 * _ipa_init_rt6_v3() - Initialize IPA routing block for IPv6.

 *

 * Return codes: 0 for success, negative value for failure

 */

int _ipa_init_rt6_v3(void)

{

	struct ipa_desc desc = { 0 };

	struct ipa_mem_buffer mem;
@@ -2026,7 +1890,12 @@ int _ipa_init_rt6_v2(void) 
	return rc;

}



int _ipa_init_flt4_v2(void)

/**

 * _ipa_init_flt4_v3() - Initialize IPA filtering block for IPv4.

 *

 * Return codes: 0 for success, negative value for failure

 */

int _ipa_init_flt4_v3(void)

{

	struct ipa_desc desc = { 0 };

	struct ipa_mem_buffer mem;
@@ -2075,7 +1944,12 @@ int _ipa_init_flt4_v2(void) 
	return rc;

}



int _ipa_init_flt6_v2(void)

/**

 * _ipa_init_flt6_v3() - Initialize IPA filtering block for IPv6.

 *

 * Return codes: 0 for success, negative value for failure

 */

int _ipa_init_flt6_v3(void)

{

	struct ipa_desc desc = { 0 };

	struct ipa_mem_buffer mem;
@@ -2179,10 +2053,6 @@ static int ipa_setup_apps_pipes(void) 
	memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params));

	sys_in.client = IPA_CLIENT_APPS_LAN_CONS;

	sys_in.desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ;

	if (ipa_ctx->ipa_hw_type == IPA_HW_v1_1) {

		sys_in.ipa_ep_cfg.hdr.hdr_a5_mux = 1;

		sys_in.ipa_ep_cfg.hdr.hdr_len = IPA_A5_MUX_HEADER_LENGTH;

	} else if (ipa_ctx->ipa_hw_type >= IPA_HW_v2_0) {

	sys_in.notify = ipa_lan_rx_cb;

	sys_in.priv = NULL;

	sys_in.ipa_ep_cfg.hdr.hdr_len = IPA_LAN_RX_HEADER_LENGTH;
@@ -2193,9 +2063,6 @@ static int ipa_setup_apps_pipes(void) 
	sys_in.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 0;

	sys_in.ipa_ep_cfg.hdr_ext.hdr_pad_to_alignment = 2;

	sys_in.ipa_ep_cfg.cfg.cs_offload_en = IPA_ENABLE_CS_OFFLOAD_DL;

	} else {

		WARN_ON(1);

	}



	/**

	 * ipa_lan_rx_cb() intended to notify the source EP about packet
@@ -2418,40 +2285,13 @@ static int ipa_get_clks(struct device *dev) 
		}

	}



	if (ipa_ctx->ipa_hw_type < IPA_HW_v2_0) {

		ipa_cnoc_clk = clk_get(dev, "iface_clk");

		if (IS_ERR(ipa_cnoc_clk)) {

			ipa_cnoc_clk = NULL;

			IPAERR("fail to get cnoc clk\n");

			return -ENODEV;

		}



		ipa_clk_src = clk_get(dev, "core_src_clk");

		if (IS_ERR(ipa_clk_src)) {

			ipa_clk_src = NULL;

			IPAERR("fail to get ipa clk src\n");

			return -ENODEV;

		}



		sys_noc_ipa_axi_clk = clk_get(dev, "bus_clk");

		if (IS_ERR(sys_noc_ipa_axi_clk)) {

			sys_noc_ipa_axi_clk = NULL;

			IPAERR("fail to get sys_noc_ipa_axi clk\n");

			return -ENODEV;

		}



		ipa_inactivity_clk = clk_get(dev, "inactivity_clk");

		if (IS_ERR(ipa_inactivity_clk)) {

			ipa_inactivity_clk = NULL;

			IPAERR("fail to get inactivity clk\n");

			return -ENODEV;

		}

	}



	return 0;

}



void _ipa_enable_clks_v2_0(void)

/**

 * _ipa_enable_clks_v3_0() - Enable IPA clocks.

 */

void _ipa_enable_clks_v3_0(void)

{

	IPADBG("enabling gcc_ipa_clk\n");

	if (ipa_clk) {
@@ -2468,55 +2308,6 @@ void _ipa_enable_clks_v2_0(void) 
		clk_prepare_enable(smmu_clk);

}



void _ipa_enable_clks_v1_1(void)

{



	if (ipa_cnoc_clk) {

		clk_prepare(ipa_cnoc_clk);

		clk_enable(ipa_cnoc_clk);

		clk_set_rate(ipa_cnoc_clk, IPA_CNOC_CLK_RATE);

	} else {

		WARN_ON(1);

	}



	if (ipa_clk_src)

		clk_set_rate(ipa_clk_src,

				ipa_ctx->curr_ipa_clk_rate);

	else

		WARN_ON(1);



	if (ipa_clk)

		clk_prepare(ipa_clk);

	else

		WARN_ON(1);



	if (sys_noc_ipa_axi_clk)

		clk_prepare(sys_noc_ipa_axi_clk);

	else

		WARN_ON(1);



	if (ipa_inactivity_clk)

		clk_prepare(ipa_inactivity_clk);

	else

		WARN_ON(1);



	if (ipa_clk)

		clk_enable(ipa_clk);

	else

		WARN_ON(1);



	if (sys_noc_ipa_axi_clk)

		clk_enable(sys_noc_ipa_axi_clk);

	else

		WARN_ON(1);



	if (ipa_inactivity_clk)

		clk_enable(ipa_inactivity_clk);

	else

		WARN_ON(1);



}



static unsigned int ipa_get_bus_vote(void)

{

	unsigned int idx = 1;
@@ -2584,7 +2375,10 @@ void _ipa_disable_clks_v1_1(void) 


}



void _ipa_disable_clks_v2_0(void)

/**

 * _ipa_disable_clks_v3_0() - Disable IPA clocks.

 */

void _ipa_disable_clks_v3_0(void)

{

	IPADBG("disabling gcc_ipa_clk\n");

	ipa_uc_notify_clk_state(false);
@@ -2719,37 +2513,6 @@ void ipa_dec_client_disable_clks(void) 
	ipa_active_clients_unlock();

}



static int ipa_setup_bam_cfg(const struct ipa_plat_drv_res *res)

{

	void *ipa_bam_mmio;

	int reg_val;

	int retval = 0;



	ipa_bam_mmio = ioremap(res->ipa_mem_base + IPA_BAM_REG_BASE_OFST,

			IPA_BAM_REMAP_SIZE);

	if (!ipa_bam_mmio)

		return -ENOMEM;

	switch (ipa_ctx->ipa_hw_type) {

	case IPA_HW_v1_1:

		reg_val = IPA_BAM_CNFG_BITS_VALv1_1;

		break;

	case IPA_HW_v2_0:

	case IPA_HW_v2_5:

	case IPA_HW_v2_6L:

		reg_val = IPA_BAM_CNFG_BITS_VALv2_0;

		break;

	default:

		retval = -EPERM;

		goto fail;

	}

	if (ipa_ctx->ipa_hw_type < IPA_HW_v2_5)

		ipa_write_reg(ipa_bam_mmio, IPA_BAM_CNFG_BITS_OFST, reg_val);

fail:

	iounmap(ipa_bam_mmio);



	return retval;

}



int ipa_set_required_perf_profile(enum ipa_voltage_level floor_voltage,

				  u32 bandwidth_mbps)

{
@@ -2833,7 +2596,6 @@ static int ipa_init_flt_block(void) 
	struct ipa_ioc_get_rt_tbl rt_lookup;

	enum ipa_ip_type ip;



	if (ipa_ctx->ipa_hw_type >= IPA_HW_v1_1) {

	size_t sz = sizeof(struct ipa_ioc_add_flt_rule) +

		   sizeof(struct ipa_flt_rule_add);
@@ -2852,7 +2614,6 @@ static int ipa_init_flt_block(void) 
				IPA_RESOURCE_NAME_MAX);

		ipa_get_rt_tbl(&rt_lookup);

		ipa_put_rt_tbl(rt_lookup.hdl);



		memset(rules, 0, sz);

		rule = &rules->rules[0];

		rules->commit = 1;
@@ -2896,7 +2657,6 @@ static int ipa_init_flt_block(void) 
		}

	}

	kfree(rules);

	}

	return result;

}
@@ -3189,6 +2949,8 @@ static int ipa_init(const struct ipa_plat_drv_res *resource_p, 
	ipa_enable_clks();



	/* setup IPA register access */

	IPADBG("Mapping 0x%x\n", resource_p->ipa_mem_base +

		ipa_ctx->ctrl->ipa_reg_base_ofst);

	ipa_ctx->mmio = ioremap(resource_p->ipa_mem_base +

			ipa_ctx->ctrl->ipa_reg_base_ofst,

			resource_p->ipa_mem_size);
@@ -3271,12 +3033,6 @@ static int ipa_init(const struct ipa_plat_drv_res *resource_p, 
	}

	IPADBG("IPA BAM is registered\n");



	if (ipa_setup_bam_cfg(resource_p)) {

		IPAERR(":bam cfg err.\n");

		result = -ENODEV;

		goto fail_flt_rule_cache;

	}



	/* init the lookaside cache */

	ipa_ctx->flt_rule_cache = kmem_cache_create("IPA FLT",

			sizeof(struct ipa_flt_entry), 0, 0, NULL);
@@ -3656,6 +3412,11 @@ static int get_ipa_dts_configuration(struct platform_device *pdev, 
	}

	IPADBG(": ipa_hw_type = %d", ipa_drv_res->ipa_hw_type);



	if (ipa_drv_res->ipa_hw_type < IPA_HW_v3_0) {

		IPAERR(":IPA version below 3.0 not supported!\n");

		return -ENODEV;

	}



	/* Get IPA HW mode */

	result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-hw-mode",

			&ipa_drv_res->ipa_hw_mode);

drivers/platform/msm/ipa/ipa_v3/ipa_client.c

+4 −10
Original line number Diff line number Diff line
@@ -32,9 +32,7 @@ int ipa_enable_data_path(u32 clnt_hdl) 
	int res = 0;



	IPADBG("Enabling data path\n");

	/* From IPA 2.0, disable HOLB */

	if ((ipa_ctx->ipa_hw_type >= IPA_HW_v2_0) &&

		IPA_CLIENT_IS_CONS(ep->client)) {

	if (IPA_CLIENT_IS_CONS(ep->client)) {

		memset(&holb_cfg, 0 , sizeof(holb_cfg));

		holb_cfg.en = IPA_HOLB_TMR_DIS;

		holb_cfg.tmr_val = 0;
@@ -63,9 +61,7 @@ int ipa_disable_data_path(u32 clnt_hdl) 
	int res = 0;



	IPADBG("Disabling data path\n");

	/* On IPA 2.0, enable HOLB in order to prevent IPA from stalling */

	if ((ipa_ctx->ipa_hw_type >= IPA_HW_v2_0) &&

		IPA_CLIENT_IS_CONS(ep->client)) {

	if (IPA_CLIENT_IS_CONS(ep->client)) {

		memset(&holb_cfg, 0, sizeof(holb_cfg));

		holb_cfg.en = IPA_HOLB_TMR_EN;

		holb_cfg.tmr_val = 0;
@@ -81,7 +77,7 @@ int ipa_disable_data_path(u32 clnt_hdl) 


	udelay(IPA_PKT_FLUSH_TO_US);

	aggr_init = ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_AGGR_N_OFST_v2_0(clnt_hdl));

			IPA_ENDP_INIT_AGGR_N_OFST_v3_0(clnt_hdl));

	if (((aggr_init & IPA_ENDP_INIT_AGGR_N_AGGR_EN_BMSK) >>

	    IPA_ENDP_INIT_AGGR_N_AGGR_EN_SHFT) == IPA_ENABLE_AGGR)

		ipa_tag_aggr_force_close(clnt_hdl);
@@ -346,9 +342,7 @@ int ipa_connect(const struct ipa_connect_params *in, struct ipa_sps_params *sps, 
		}

	}



	if ((ipa_ctx->ipa_hw_type == IPA_HW_v2_0 ||

		ipa_ctx->ipa_hw_type == IPA_HW_v2_5) &&

		IPA_CLIENT_IS_USB_CONS(in->client))

	if (IPA_CLIENT_IS_USB_CONS(in->client))

		ep->connect.event_thresh = IPA_USB_EVENT_THRESHOLD;

	else

		ep->connect.event_thresh = IPA_EVENT_THRESHOLD;

drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c

+43 −118
Original line number Diff line number Diff line
@@ -105,23 +105,13 @@ static struct dentry *dfile_rm_stats; 
static char dbg_buff[IPA_MAX_MSG_LEN];

static s8 ep_reg_idx;



int _ipa_read_gen_reg_v1_1(char *buff, int max_len)

{

	return scnprintf(dbg_buff, IPA_MAX_MSG_LEN,

			"IPA_VERSION=0x%x\n"

			"IPA_COMP_HW_VERSION=0x%x\n"

			"IPA_ROUTE=0x%x\n"

			"IPA_FILTER=0x%x\n"

			"IPA_SHARED_MEM_SIZE=0x%x\n",

			ipa_read_reg(ipa_ctx->mmio, IPA_VERSION_OFST),

			ipa_read_reg(ipa_ctx->mmio, IPA_COMP_HW_VERSION_OFST),

			ipa_read_reg(ipa_ctx->mmio, IPA_ROUTE_OFST_v1_1),

			ipa_read_reg(ipa_ctx->mmio, IPA_FILTER_OFST_v1_1),

			ipa_read_reg(ipa_ctx->mmio,

					IPA_SHARED_MEM_SIZE_OFST_v1_1));

}



int _ipa_read_gen_reg_v2_0(char *buff, int max_len)

/**

 * _ipa_read_gen_reg_v3_0() - Reads and prints IPA general configuration

 *	registers

 *

 * Returns the number of characters printed

 */

int _ipa_read_gen_reg_v3_0(char *buff, int max_len)

{

	return scnprintf(dbg_buff, IPA_MAX_MSG_LEN,

			"IPA_VERSION=0x%x\n"
@@ -132,16 +122,16 @@ int _ipa_read_gen_reg_v2_0(char *buff, int max_len) 
			"IPA_SHARED_MEM_SIZE=0x%x\n",

			ipa_read_reg(ipa_ctx->mmio, IPA_VERSION_OFST),

			ipa_read_reg(ipa_ctx->mmio, IPA_COMP_HW_VERSION_OFST),

			ipa_read_reg(ipa_ctx->mmio, IPA_ROUTE_OFST_v1_1),

			ipa_read_reg(ipa_ctx->mmio, IPA_FILTER_OFST_v1_1),

			ipa_read_reg(ipa_ctx->mmio, IPA_ROUTE_OFST_v3_0),

			ipa_read_reg(ipa_ctx->mmio, IPA_FILTER_OFST_v3_0),

			ipa_read_reg_field(ipa_ctx->mmio,

				IPA_SHARED_MEM_SIZE_OFST_v2_0,

				IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK_v2_0,

				IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_SHFT_v2_0),

				IPA_SHARED_MEM_SIZE_OFST_v3_0,

				IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK_v3_0,

				IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_SHFT_v3_0),

			ipa_read_reg_field(ipa_ctx->mmio,

				IPA_SHARED_MEM_SIZE_OFST_v2_0,

				IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_BMSK_v2_0,

				IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_SHFT_v2_0));

				IPA_SHARED_MEM_SIZE_OFST_v3_0,

				IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_BMSK_v3_0,

				IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_SHFT_v3_0));

}



static ssize_t ipa_read_gen_reg(struct file *file, char __user *ubuf,
@@ -230,37 +220,12 @@ static ssize_t ipa_write_ep_reg(struct file *file, const char __user *buf, 
	return count;

}



int _ipa_read_ep_reg_v1_1(char *buf, int max_len, int pipe)

{

	return scnprintf(dbg_buff, IPA_MAX_MSG_LEN,

			"IPA_ENDP_INIT_NAT_%u=0x%x\n"

			"IPA_ENDP_INIT_HDR_%u=0x%x\n"

			"IPA_ENDP_INIT_MODE_%u=0x%x\n"

			"IPA_ENDP_INIT_AGGR_%u=0x%x\n"

			"IPA_ENDP_INIT_ROUTE_%u=0x%x\n"

			"IPA_ENDP_INIT_CTRL_%u=0x%x\n"

			"IPA_ENDP_INIT_HOL_EN_%u=0x%x\n"

			"IPA_ENDP_INIT_HOL_TIMER_%u=0x%x\n",

			pipe, ipa_read_reg(ipa_ctx->mmio,

				IPA_ENDP_INIT_NAT_N_OFST_v1_1(pipe)),

			pipe, ipa_read_reg(ipa_ctx->mmio,

				IPA_ENDP_INIT_HDR_N_OFST_v1_1(pipe)),

			pipe, ipa_read_reg(ipa_ctx->mmio,

				IPA_ENDP_INIT_MODE_N_OFST_v1_1(pipe)),

			pipe, ipa_read_reg(ipa_ctx->mmio,

				IPA_ENDP_INIT_AGGR_N_OFST_v1_1(pipe)),

			pipe, ipa_read_reg(ipa_ctx->mmio,

				IPA_ENDP_INIT_ROUTE_N_OFST_v1_1(pipe)),

			pipe, ipa_read_reg(ipa_ctx->mmio,

				IPA_ENDP_INIT_CTRL_N_OFST(pipe)),

			pipe, ipa_read_reg(ipa_ctx->mmio,

				IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v1_1(pipe)),

			pipe, ipa_read_reg(ipa_ctx->mmio,

				IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v1_1(pipe))

				);

}



int _ipa_read_ep_reg_v2_0(char *buf, int max_len, int pipe)

/**

 * _ipa_read_ep_reg_v3_0() - Reads and prints endpoint configuration registers

 *

 * Returns the number of characters printed

 */

int _ipa_read_ep_reg_v3_0(char *buf, int max_len, int pipe)

{

	return scnprintf(

		dbg_buff, IPA_MAX_MSG_LEN,
@@ -276,25 +241,25 @@ int _ipa_read_ep_reg_v2_0(char *buf, int max_len, int pipe) 
		"IPA_ENDP_INIT_DEAGGR_%u=0x%x\n"

		"IPA_ENDP_INIT_CFG_%u=0x%x\n",

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_NAT_N_OFST_v2_0(pipe)),

			IPA_ENDP_INIT_NAT_N_OFST_v3_0(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_HDR_N_OFST_v2_0(pipe)),

			IPA_ENDP_INIT_HDR_N_OFST_v3_0(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_HDR_EXT_n_OFST_v2_0(pipe)),

			IPA_ENDP_INIT_HDR_EXT_n_OFST_v3_0(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_MODE_N_OFST_v2_0(pipe)),

			IPA_ENDP_INIT_MODE_N_OFST_v3_0(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_AGGR_N_OFST_v2_0(pipe)),

			IPA_ENDP_INIT_AGGR_N_OFST_v3_0(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_ROUTE_N_OFST_v2_0(pipe)),

			IPA_ENDP_INIT_ROUTE_N_OFST_v3_0(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_CTRL_N_OFST(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v2_0(pipe)),

			IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v3_0(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v2_0(pipe)),

			IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v3_0(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_DEAGGR_n_OFST_v2_0(pipe)),

			IPA_ENDP_INIT_DEAGGR_n_OFST_v3_0(pipe)),

		pipe, ipa_read_reg(ipa_ctx->mmio,

			IPA_ENDP_INIT_CFG_n_OFST(pipe)));

}
@@ -853,7 +818,6 @@ static ssize_t ipa_read_stats(struct file *file, char __user *ubuf, 
	for (i = 0; i < ipa_ctx->ipa_num_pipes; i++)

		connect |= (ipa_ctx->ep[i].valid << i);



	if (ipa_ctx->ipa_hw_type >= IPA_HW_v2_0) {

		nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN,

			"sw_tx=%u\n"

			"hw_tx=%u\n"
@@ -891,32 +855,6 @@ static ssize_t ipa_read_stats(struct file *file, char __user *ubuf, 
				ipa_ctx->stats.rx_excp_pkts[i]);

			cnt += nbytes;

		}

	} else{

		nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN,

			"sw_tx=%u\n"

			"hw_tx=%u\n"

			"rx=%u\n"

			"rx_repl_repost=%u\n"

			"rx_q_len=%u\n"

			"act_clnt=%u\n"

			"con_clnt_bmap=0x%x\n",

			ipa_ctx->stats.tx_sw_pkts,

			ipa_ctx->stats.tx_hw_pkts,

			ipa_ctx->stats.rx_pkts,

			ipa_ctx->stats.rx_repl_repost,

			ipa_ctx->stats.rx_q_len,

			ipa_ctx->ipa_active_clients.cnt,

			connect);

	cnt += nbytes;



		for (i = 0; i < MAX_NUM_EXCP; i++) {

			nbytes = scnprintf(dbg_buff + cnt,

				IPA_MAX_MSG_LEN - cnt,

				"rx_excp[%u:%35s]=%u\n", i, ipa_excp_name[i],

				ipa_ctx->stats.rx_excp_pkts[i]);

			cnt += nbytes;

		}

	}



	return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt);

}
@@ -1175,23 +1113,17 @@ static ssize_t ipa_read_wdi(struct file *file, char __user *ubuf, 
	return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt);

}



void _ipa_write_dbg_cnt_v1_1(int option)

{

	if (option == 1)

		ipa_write_reg(ipa_ctx->mmio, IPA_DEBUG_CNT_CTRL_N_OFST_v1_1(0),

				IPA_DBG_CNTR_ON);

	else

		ipa_write_reg(ipa_ctx->mmio, IPA_DEBUG_CNT_CTRL_N_OFST_v1_1(0),

				IPA_DBG_CNTR_OFF);

}



void _ipa_write_dbg_cnt_v2_0(int option)

/**

 * _ipa_write_dbg_cnt_v3_0() - Configure IPA debug counter register

 *

 */

void _ipa_write_dbg_cnt_v3_0(int option)

{

	if (option == 1)

		ipa_write_reg(ipa_ctx->mmio, IPA_DEBUG_CNT_CTRL_N_OFST_v2_0(0),

		ipa_write_reg(ipa_ctx->mmio, IPA_DEBUG_CNT_CTRL_N_OFST_v3_0(0),

				IPA_DBG_CNTR_ON);

	else

		ipa_write_reg(ipa_ctx->mmio, IPA_DEBUG_CNT_CTRL_N_OFST_v2_0(0),

		ipa_write_reg(ipa_ctx->mmio, IPA_DEBUG_CNT_CTRL_N_OFST_v3_0(0),

				IPA_DBG_CNTR_OFF);

}
@@ -1219,23 +1151,16 @@ static ssize_t ipa_write_dbg_cnt(struct file *file, const char __user *buf, 
	return count;

}



int _ipa_read_dbg_cnt_v1_1(char *buf, int max_len)

{

	int regval;



	regval = ipa_read_reg(ipa_ctx->mmio,

			IPA_DEBUG_CNT_REG_N_OFST_v1_1(0));



	return scnprintf(buf, max_len,

			"IPA_DEBUG_CNT_REG_0=0x%x\n", regval);

}



int _ipa_read_dbg_cnt_v2_0(char *buf, int max_len)

/**

 * _ipa_write_dbg_cnt_v3_0() - Read IPA debug counter register

 *

 */

int _ipa_read_dbg_cnt_v3_0(char *buf, int max_len)

{

	int regval;



	regval = ipa_read_reg(ipa_ctx->mmio,

			IPA_DEBUG_CNT_REG_N_OFST_v2_0(0));

			IPA_DEBUG_CNT_REG_N_OFST_v3_0(0));



	return scnprintf(buf, max_len,

			"IPA_DEBUG_CNT_REG_0=0x%x\n", regval);