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Commit 249535d8 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Jonathan Cameron
Browse files

iio: adc: exynos_adc: add support for s3c64xx adc 



The ADC in s3c64xx is almost the same as exynosv1, but
has a different 'select' method. Adding this here will be
helpful to move over the existing s3c64xx platform from the
legacy plat-samsung/adc driver to the new exynos-adc.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarJonathan Cameron <jic23@kernel.org>
parent 44d6f2ef

Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ Required properties: 
				future controllers.

			Must be "samsung,exynos3250-adc" for

				controllers compatible with ADC of Exynos3250.

			Must be "samsung,s3c6410-adc" for

				the ADC in s3c6410 and compatibles

- reg:			Contains ADC register address range (base address and

			length) and the address of the phy enable register.

- interrupts: 		Contains the interrupt information for the timer. The

drivers/iio/adc/exynos_adc.c

+27 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 
#include <linux/iio/machine.h>

#include <linux/iio/driver.h>



/* EXYNOS4412/5250 ADC_V1 registers definitions */

/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */

#define ADC_V1_CON(x)		((x) + 0x00)

#define ADC_V1_DLY(x)		((x) + 0x08)

#define ADC_V1_DATX(x)		((x) + 0x0C)
@@ -61,6 +61,9 @@ 
#define ADC_V1_CON_PRSCLV(x)	(((x) & 0xFF) << 6)

#define ADC_V1_CON_STANDBY	(1u << 2)



/* Bit definitions for S3C2410 ADC */

#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)



/* Bit definitions for ADC_V2 */

#define ADC_V2_CON1_SOFT_RESET	(1u << 2)
@@ -217,6 +220,26 @@ static const struct exynos_adc_data exynos_adc_v1_data = { 
	.start_conv	= exynos_adc_v1_start_conv,

};



static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,

					  unsigned long addr)

{

	u32 con1;



	con1 = readl(ADC_V1_CON(info->regs));

	con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);

	con1 |= ADC_S3C2410_CON_SELMUX(addr);

	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));

}



static struct exynos_adc_data const exynos_adc_s3c64xx_data = {

	.num_channels	= MAX_ADC_V1_CHANNELS,



	.init_hw	= exynos_adc_v1_init_hw,

	.exit_hw	= exynos_adc_v1_exit_hw,

	.clear_irq	= exynos_adc_v1_clear_irq,

	.start_conv	= exynos_adc_s3c64xx_start_conv,

};



static void exynos_adc_v2_init_hw(struct exynos_adc *info)

{

	u32 con1, con2;
@@ -285,6 +308,9 @@ static const struct exynos_adc_data exynos3250_adc_data = { 


static const struct of_device_id exynos_adc_match[] = {

	{

		.compatible = "samsung,s3c6410-adc",

		.data = &exynos_adc_s3c64xx_data,

	}, {

		.compatible = "samsung,exynos-adc-v1",

		.data = &exynos_adc_v1_data,

	}, {