rtlwifi: rtl8192se: Update driver to match vendor driver of 2013.02.07 (2455c92c) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/net/wireless/rtlwifi/rtl8192se/def.h

+0 −7

Original line number	Diff line number	Diff line
		@@ -36,9 +36,6 @@
		#define SHORT_SLOT_TIME 9
		#define NON_SHORT_SLOT_TIME 20

		/* Rx smooth factor */
		#define RX_SMOOTH_FACTOR 20

		/* Queue Select Value in TxDesc */
		#define QSLT_BK 0x2
		#define QSLT_BE 0x0
		@@ -49,10 +46,6 @@
		#define QSLT_MGNT 0x12
		#define QSLT_CMD 0x13

		#define PHY_RSSI_SLID_WIN_MAX 100
		#define PHY_LINKQUALITY_SLID_WIN_MAX 20
		#define PHY_BEACON_RSSI_SLID_WIN_MAX 10

		/* Tx Desc */
		#define TX_DESC_SIZE_RTL8192S (16 * 4)
		#define TX_CMDDESC_SIZE_RTL8192S (16 * 4)

drivers/net/wireless/rtlwifi/rtl8192se/dm.c

+25 −10

Original line number	Diff line number	Diff line
		@@ -163,6 +163,7 @@ static void _rtl92s_dm_txpowertracking_callback_thermalmeter(
		struct rtl_priv *rtlpriv = rtl_priv(hw);
		struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
		u8 thermalvalue = 0;
		u32 fw_cmd = 0;

		rtlpriv->dm.txpower_trackinginit = true;

		@@ -175,7 +176,19 @@ static void _rtl92s_dm_txpowertracking_callback_thermalmeter(

		if (thermalvalue) {
		rtlpriv->dm.thermalvalue = thermalvalue;
		if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
		rtl92s_phy_set_fw_cmd(hw, FW_CMD_TXPWR_TRACK_THERMAL);
		} else {
		fw_cmd = (FW_TXPWR_TRACK_THERMAL \|
		(rtlpriv->efuse.thermalmeter[0] << 8) \|
		(thermalvalue << 16));

		RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
		"Write to FW Thermal Val = 0x%x\n", fw_cmd);

		rtl_write_dword(rtlpriv, WFM5, fw_cmd);
		rtl92s_phy_chk_fwcmd_iodone(hw);
		}
		}

		rtlpriv->dm.txpowercount = 0;
		@@ -217,11 +230,10 @@ static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
		struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
		struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
		struct rate_adaptive *ra = &(rtlpriv->ra);

		struct ieee80211_sta *sta = NULL;
		u32 low_rssi_thresh = 0;
		u32 middle_rssi_thresh = 0;
		u32 high_rssi_thresh = 0;
		struct ieee80211_sta *sta = NULL;

		if (is_hal_stop(rtlhal))
		return;
		@@ -229,14 +241,12 @@ static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
		if (!rtlpriv->dm.useramask)
		return;

		if (!rtlpriv->dm.inform_fw_driverctrldm) {
		if (hal_get_firmwareversion(rtlpriv) >= 61 &&
		!rtlpriv->dm.inform_fw_driverctrldm) {
		rtl92s_phy_set_fw_cmd(hw, FW_CMD_CTRL_DM_BY_DRIVER);
		rtlpriv->dm.inform_fw_driverctrldm = true;
		}

		rcu_read_lock();
		if (mac->opmode == NL80211_IFTYPE_STATION)
		sta = get_sta(hw, mac->vif, mac->bssid);
		if ((mac->link_state == MAC80211_LINKED) &&
		(mac->opmode == NL80211_IFTYPE_STATION)) {
		switch (ra->pre_ratr_state) {
		@@ -285,12 +295,16 @@ static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
		rtlpriv->dm.undec_sm_pwdb, ra->ratr_state,
		ra->pre_ratr_state, ra->ratr_state);

		rcu_read_lock();
		sta = rtl_find_sta(hw, mac->bssid);
		if (sta)
		rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
		ra->ratr_state);
		rcu_read_unlock();

		ra->pre_ratr_state = ra->ratr_state;
		}
		}
		rcu_read_unlock();
		}

		static void _rtl92s_dm_switch_baseband_mrc(struct ieee80211_hw *hw)
		@@ -370,7 +384,8 @@ static void _rtl92s_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
		ra->ratr_state = DM_RATR_STA_MAX;
		ra->pre_ratr_state = DM_RATR_STA_MAX;

		if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
		if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER &&
		hal_get_firmwareversion(rtlpriv) >= 60)
		rtlpriv->dm.useramask = true;
		else
		rtlpriv->dm.useramask = false;

drivers/net/wireless/rtlwifi/rtl8192se/hw.c

+86 −38

Original line number	Diff line number	Diff line
		@@ -400,6 +400,39 @@ void rtl92se_set_hw_reg(struct ieee80211_hw hw, u8 variable, u8 val)

		break;
		}
		case HW_VAR_FW_LPS_ACTION: {
		bool enter_fwlps = ((bool )val);
		u8 rpwm_val, fw_pwrmode;
		bool fw_current_inps;

		if (enter_fwlps) {
		rpwm_val = 0x02; /* RF off */
		fw_current_inps = true;
		rtlpriv->cfg->ops->set_hw_reg(hw,
		HW_VAR_FW_PSMODE_STATUS,
		(u8 *)(&fw_current_inps));
		rtlpriv->cfg->ops->set_hw_reg(hw,
		HW_VAR_H2C_FW_PWRMODE,
		(u8 *)(&ppsc->fwctrl_psmode));

		rtlpriv->cfg->ops->set_hw_reg(hw,
		HW_VAR_SET_RPWM,
		(u8 *)(&rpwm_val));
		} else {
		rpwm_val = 0x0C; /* RF on */
		fw_pwrmode = FW_PS_ACTIVE_MODE;
		fw_current_inps = false;
		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
		(u8 *)(&rpwm_val));
		rtlpriv->cfg->ops->set_hw_reg(hw,
		HW_VAR_H2C_FW_PWRMODE,
		(u8 *)(&fw_pwrmode));

		rtlpriv->cfg->ops->set_hw_reg(hw,
		HW_VAR_FW_PSMODE_STATUS,
		(u8 *)(&fw_current_inps));
		}
		break; }
		default:
		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
		"switch case not processed\n");
		@@ -438,7 +471,7 @@ void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)

		}

		static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
		static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data)
		{
		struct rtl_priv *rtlpriv = rtl_priv(hw);
		u8 waitcount = 100;
		@@ -547,7 +580,7 @@ static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
		tmpu1b &= ~(BIT(6) \| BIT(7));

		/* Set failed, return to prevent hang. */
		if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
		if (!_rtl92se_halset_sysclk(hw, tmpu1b))
		return;
		}

		@@ -650,7 +683,7 @@ static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)

		tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
		tmpu1b = ((tmpu1b \| BIT(7)) & (~BIT(6)));
		if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
		if (!_rtl92se_halset_sysclk(hw, tmpu1b))
		return; /* Set failed, return to prevent hang. */

		rtl_write_word(rtlpriv, CMDR, 0x07FC);
		@@ -967,6 +1000,15 @@ int rtl92se_hw_init(struct ieee80211_hw *hw)
		return rtstatus;
		}

		/* because last function modify RCR, so we update
		* rcr var here, or TP will unstable for receive_config
		* is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
		* RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
		*/
		rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
		rtlpci->receive_config &= ~(RCR_ACRC32 \| RCR_AICV);
		rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);

		/* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
		/* We must set flag avoid BB/RF config period later!! */
		rtl_write_dword(rtlpriv, CMDR, 0x37FC);
		@@ -982,25 +1024,6 @@ int rtl92se_hw_init(struct ieee80211_hw *hw)

		rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;

		/* RF Power Save */
		#if 0
		/* H/W or S/W RF OFF before sleep. */
		if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
		u32 rfoffreason = rtlpriv->psc.rfoff_reason;

		rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
		rtlpriv->psc.rfpwr_state = ERFON;
		/* FIXME: check spinlocks if this block is uncommented */
		rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason);
		} else {
		/* gpio radio on/off is out of adapter start */
		if (rtlpriv->psc.hwradiooff == false) {
		rtlpriv->psc.rfpwr_state = ERFON;
		rtlpriv->psc.rfoff_reason = 0;
		}
		}
		#endif

		/* Before RF-R/W we must execute the IO from Scott's suggestion. */
		rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
		if (rtlhal->version == VERSION_8192S_ACUT)
		@@ -1058,7 +1081,22 @@ int rtl92se_hw_init(struct ieee80211_hw *hw)

		/* We enable high power and RA related mechanism after NIC
		* initialized. */
		if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
		/* Fw v.53 and later. */
		rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
		} else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
		/* Fw v.52. */
		rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT);
		rtl92s_phy_chk_fwcmd_iodone(hw);
		} else {
		/* Compatible earlier FW version. */
		rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
		rtl92s_phy_chk_fwcmd_iodone(hw);
		rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
		rtl92s_phy_chk_fwcmd_iodone(hw);
		rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
		rtl92s_phy_chk_fwcmd_iodone(hw);
		}

		/* Add to prevent ASPM bug. */
		/* Always enable hst and NIC clock request. */
		@@ -1229,7 +1267,6 @@ void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
		synchronize_irq(rtlpci->pdev->irq);
		}


		static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
		{
		struct rtl_priv *rtlpriv = rtl_priv(hw);
		@@ -1999,6 +2036,8 @@ static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
		ratr_value = sta->supp_rates[1] << 4;
		else
		ratr_value = sta->supp_rates[0];
		if (mac->opmode == NL80211_IFTYPE_ADHOC)
		ratr_value = 0xfff;
		ratr_value \|= (sta->ht_cap.mcs.rx_mask[1] << 20 \|
		sta->ht_cap.mcs.rx_mask[0] << 12);
		switch (wirelessmode) {
		@@ -2112,6 +2151,8 @@ static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
		ratr_bitmap = sta->supp_rates[1] << 4;
		else
		ratr_bitmap = sta->supp_rates[0];
		if (mac->opmode == NL80211_IFTYPE_ADHOC)
		ratr_bitmap = 0xfff;
		ratr_bitmap \|= (sta->ht_cap.mcs.rx_mask[1] << 20 \|
		sta->ht_cap.mcs.rx_mask[0] << 12);
		switch (wirelessmode) {
		@@ -2200,6 +2241,7 @@ static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
		ratr_bitmap &= 0x0f8ff0ff;
		break;
		}
		sta_entry->ratr_index = ratr_index;

		if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
		ratr_bitmap &= 0x0FFFFFFF;
		@@ -2438,23 +2480,9 @@ void rtl92se_set_key(struct ieee80211_hw hw, u32 key_index, u8 p_macaddr,
		rtl_cam_del_entry(hw, p_macaddr);
		rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
		} else {
		RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
		"The insert KEY length is %d\n",
		rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
		RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
		"The insert KEY is %x %x\n",
		rtlpriv->sec.key_buf[0][0],
		rtlpriv->sec.key_buf[0][1]);

		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
		"add one entry\n");
		if (is_pairwise) {
		RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
		"Pairwise Key content",
		rtlpriv->sec.pairwise_key,
		rtlpriv->sec.
		key_len[PAIRWISE_KEYIDX]);

		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
		"set Pairwise key\n");

		@@ -2502,3 +2530,23 @@ void rtl92se_resume(struct ieee80211_hw *hw)
		pci_write_config_dword(rtlpci->pdev, 0x40,
		val & 0xffff00ff);
		}

		/* Turn on AAP (RCR:bit 0) for promicuous mode. */
		void rtl92se_allow_all_destaddr(struct ieee80211_hw *hw,
		bool allow_all_da, bool write_into_reg)
		{
		struct rtl_priv *rtlpriv = rtl_priv(hw);
		struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));

		if (allow_all_da) /* Set BIT0 */
		rtlpci->receive_config \|= RCR_AAP;
		else /* Clear BIT0 */
		rtlpci->receive_config &= ~RCR_AAP;

		if (write_into_reg)
		rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);

		RT_TRACE(rtlpriv, COMP_TURBO \| COMP_INIT, DBG_LOUD,
		"receive_config=0x%08X, write_into_reg=%d\n",
		rtlpci->receive_config, write_into_reg);
		}

drivers/net/wireless/rtlwifi/rtl8192se/hw.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -74,6 +74,7 @@ void rtl92se_set_key(struct ieee80211_hw *hw,
		u8 enc_algo, bool is_wepkey, bool clear_all);
		void rtl92se_suspend(struct ieee80211_hw *hw);
		void rtl92se_resume(struct ieee80211_hw *hw);
		void rtl92se_allow_all_destaddr(struct ieee80211_hw *hw,
		bool allow_all_da, bool write_into_reg);

		#endif

drivers/net/wireless/rtlwifi/rtl8192se/phy.c

+42 −19

Original line number	Diff line number	Diff line
		@@ -1307,6 +1307,8 @@ static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
		if (is_hal_stop(rtlhal))
		return;

		if (hal_get_firmwareversion(rtlpriv) < 0x34)
		goto skip;
		/* We re-map RA related CMD IO to combinational ones */
		/* if FW version is v.52 or later. */
		switch (rtlhal->current_fwcmd_io) {
		@@ -1320,6 +1322,7 @@ static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
		break;
		}

		skip:
		switch (rtlhal->current_fwcmd_io) {
		case FW_CMD_RA_RESET:
		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
		@@ -1440,7 +1443,7 @@ bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
		struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
		u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
		u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
		bool bPostProcessing = false;
		bool postprocessing = false;

		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
		"Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
		@@ -1449,6 +1452,7 @@ bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
		do {
		/* We re-map to combined FW CMD ones if firmware version */
		/* is v.53 or later. */
		if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
		switch (fw_cmdio) {
		case FW_CMD_RA_REFRESH_N:
		fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
		@@ -1459,6 +1463,14 @@ bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
		default:
		break;
		}
		} else {
		if ((fw_cmdio == FW_CMD_IQK_ENABLE) \|\|
		(fw_cmdio == FW_CMD_RA_REFRESH_N) \|\|
		(fw_cmdio == FW_CMD_RA_REFRESH_BG)) {
		postprocessing = true;
		break;
		}
		}

		/* If firmware version is v.62 or later,
		* use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
		@@ -1588,19 +1600,19 @@ bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
		fw_cmdmap &= ~FW_DIG_ENABLE_CTL;

		FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
		bPostProcessing = true;
		postprocessing = true;
		break;
		case FW_CMD_PAUSE_DM_BY_SCAN:
		fw_cmdmap &= ~(FW_DIG_ENABLE_CTL \|
		FW_HIGH_PWR_ENABLE_CTL \|
		FW_SS_CTL);
		FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
		bPostProcessing = true;
		postprocessing = true;
		break;
		case FW_CMD_HIGH_PWR_DISABLE:
		fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
		FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
		bPostProcessing = true;
		postprocessing = true;
		break;
		case FW_CMD_HIGH_PWR_ENABLE:
		if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
		@@ -1608,7 +1620,7 @@ bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
		fw_cmdmap \|= (FW_HIGH_PWR_ENABLE_CTL \|
		FW_SS_CTL);
		FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
		bPostProcessing = true;
		postprocessing = true;
		}
		break;
		case FW_CMD_DIG_MODE_FA:
		@@ -1629,14 +1641,15 @@ bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
		default:
		/* Pass to original FW CMD processing callback
		* routine. */
		bPostProcessing = true;
		postprocessing = true;
		break;
		}
		} while (false);

		/* We shall post processing these FW CMD if
		* variable bPostProcessing is set. */
		if (bPostProcessing && !rtlhal->set_fwcmd_inprogress) {
		* variable postprocessing is set.
		*/
		if (postprocessing && !rtlhal->set_fwcmd_inprogress) {
		rtlhal->set_fwcmd_inprogress = true;
		/* Update current FW Cmd for callback use. */
		rtlhal->current_fwcmd_io = fw_cmdio;
		@@ -1697,8 +1710,18 @@ void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)

		}

		void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 BeaconInterval)
		void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval)
		{
		struct rtl_priv *rtlpriv = rtl_priv(hw);
		rtl_write_dword(rtlpriv, WFM5, 0xF1000000 \| (BeaconInterval << 8));
		u32 new_bcn_num = 0;

		if (hal_get_firmwareversion(rtlpriv) >= 0x33) {
		/* Fw v.51 and later. */
		rtl_write_dword(rtlpriv, WFM5, 0xF1000000 \|
		(beaconinterval << 8));
		} else {
		new_bcn_num = beaconinterval * 32 - 64;
		rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num);
		rtl_write_dword(rtlpriv, WFM3, 0xB026007C);
		}
		}