Merge remote-tracking branch 'lts/linux-3.18.y' into linux-linaro-lsk-v3.18 (24284529) · Commits · e / devices / android_kernel_xiaomi_markw

Makefile

+1 −1

Original line number	Diff line number	Diff line
		VERSION = 3
		PATCHLEVEL = 18
		SUBLEVEL = 29
		SUBLEVEL = 30
		EXTRAVERSION =
		NAME = Diseased Newt

arch/arm/boot/dts/dra7.dtsi

+71 −0

Original line number	Diff line number	Diff line
		@@ -34,6 +34,8 @@
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		ethernet0 = &cpsw_emac0;
		ethernet1 = &cpsw_emac1;
		};

		timer {
		@@ -1265,6 +1267,75 @@
		ti,irqs-skip = <10 133 139 140>;
		ti,irqs-safe-map = <0>;
		};

		mac: ethernet@4a100000 {
		compatible = "ti,cpsw";
		ti,hwmods = "gmac";
		clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
		clock-names = "fck", "cpts";
		cpdma_channels = <8>;
		ale_entries = <1024>;
		bd_ram_size = <0x2000>;
		no_bd_ram = <0>;
		rx_descs = <64>;
		mac_control = <0x20>;
		slaves = <2>;
		active_slave = <0>;
		cpts_clock_mult = <0x80000000>;
		cpts_clock_shift = <29>;
		reg = <0x48484000 0x1000
		0x48485200 0x2E00>;
		#address-cells = <1>;
		#size-cells = <1>;

		/*
		* Do not allow gating of cpsw clock as workaround
		* for errata i877. Keeping internal clock disabled
		* causes the device switching characteristics
		* to degrade over time and eventually fail to meet
		* the data manual delay time/skew specs.
		*/
		ti,no-idle;

		/*
		* rx_thresh_pend
		* rx_pend
		* tx_pend
		* misc_pend
		*/
		interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
		ranges;
		status = "disabled";

		davinci_mdio: mdio@48485000 {
		compatible = "ti,davinci_mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		ti,hwmods = "davinci_mdio";
		bus_freq = <1000000>;
		reg = <0x48485000 0x100>;
		};

		cpsw_emac0: slave@48480200 {
		/* Filled in by U-Boot */
		mac-address = [ 00 00 00 00 00 00 ];
		};

		cpsw_emac1: slave@48480300 {
		/* Filled in by U-Boot */
		mac-address = [ 00 00 00 00 00 00 ];
		};

		phy_sel: cpsw-phy-sel@4a002554 {
		compatible = "ti,dra7xx-cpsw-phy-sel";
		reg= <0x4a002554 0x4>;
		reg-names = "gmii-sel";
		};
		};

		};
		};

arch/mips/Kconfig

+1 −1

Original line number	Diff line number	Diff line
		@@ -2048,7 +2048,7 @@ config MIPS_CMP

		config MIPS_CPS
		bool "MIPS Coherent Processing System support"
		depends on SYS_SUPPORTS_MIPS_CPS && !64BIT
		depends on SYS_SUPPORTS_MIPS_CPS
		select MIPS_CM
		select MIPS_CPC
		select MIPS_CPS_PM if HOTPLUG_CPU

arch/powerpc/kvm/book3s_hv_rmhandlers.S

+14 −0

Original line number	Diff line number	Diff line
		@@ -1284,6 +1284,20 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
		std r6, VCPU_ACOP(r9)
		stw r7, VCPU_GUEST_PID(r9)
		std r8, VCPU_WORT(r9)
		/*
		* Restore various registers to 0, where non-zero values
		* set by the guest could disrupt the host.
		*/
		li r0, 0
		mtspr SPRN_IAMR, r0
		mtspr SPRN_CIABR, r0
		mtspr SPRN_DAWRX, r0
		mtspr SPRN_TCSCR, r0
		mtspr SPRN_WORT, r0
		/* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
		li r0, 1
		sldi r0, r0, 31
		mtspr SPRN_MMCRS, r0
		8:

		/* Save and reset AMR and UAMOR before turning on the MMU */

arch/x86/kvm/vmx.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -1600,6 +1600,13 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
		return;
		}
		break;
		case MSR_IA32_PEBS_ENABLE:
		/* PEBS needs a quiescent period after being disabled (to write
		* a record). Disabling PEBS through VMX MSR swapping doesn't
		* provide that period, so a CPU could write host's record into
		* guest's memory.
		*/
		wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
		}

		for (i = 0; i < m->nr; ++i)