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Commit 241682c8 authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Olof Johansson
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arm/tegra: pinmux tables and definitions for tegra30 



Define the pinmuxing and pindrive tables for tegra30. The pinmux table defines
the available functions for each pinmux group. The pindrive table defines the
default pullup or pulldowns for each group.

Derived from code by Scott Williams (scwilliams@nvidia.com)

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-by: default avatarColin Cross <ccross@android.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 31e37a18

arch/arm/mach-tegra/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o 
obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-tegra20-tables.o

obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= pinmux-tegra30-tables.o

obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o

obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o

obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o

arch/arm/mach-tegra/include/mach/pinmux-tegra30.h

0 → 100644
+320 −0
Original line number Diff line number Diff line 
/*

 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h

 *

 * Copyright (C) 2010 Google, Inc.

 * Copyright (C) 2010,2011 Nvidia, Inc.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and

 * may be copied, distributed, and modified under those terms.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */



#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H

#define __MACH_TEGRA_PINMUX_TEGRA30_H



enum tegra_pingroup {

	TEGRA_PINGROUP_ULPI_DATA0 = 0,

	TEGRA_PINGROUP_ULPI_DATA1,

	TEGRA_PINGROUP_ULPI_DATA2,

	TEGRA_PINGROUP_ULPI_DATA3,

	TEGRA_PINGROUP_ULPI_DATA4,

	TEGRA_PINGROUP_ULPI_DATA5,

	TEGRA_PINGROUP_ULPI_DATA6,

	TEGRA_PINGROUP_ULPI_DATA7,

	TEGRA_PINGROUP_ULPI_CLK,

	TEGRA_PINGROUP_ULPI_DIR,

	TEGRA_PINGROUP_ULPI_NXT,

	TEGRA_PINGROUP_ULPI_STP,

	TEGRA_PINGROUP_DAP3_FS,

	TEGRA_PINGROUP_DAP3_DIN,

	TEGRA_PINGROUP_DAP3_DOUT,

	TEGRA_PINGROUP_DAP3_SCLK,

	TEGRA_PINGROUP_GPIO_PV0,

	TEGRA_PINGROUP_GPIO_PV1,

	TEGRA_PINGROUP_SDMMC1_CLK,

	TEGRA_PINGROUP_SDMMC1_CMD,

	TEGRA_PINGROUP_SDMMC1_DAT3,

	TEGRA_PINGROUP_SDMMC1_DAT2,

	TEGRA_PINGROUP_SDMMC1_DAT1,

	TEGRA_PINGROUP_SDMMC1_DAT0,

	TEGRA_PINGROUP_GPIO_PV2,

	TEGRA_PINGROUP_GPIO_PV3,

	TEGRA_PINGROUP_CLK2_OUT,

	TEGRA_PINGROUP_CLK2_REQ,

	TEGRA_PINGROUP_LCD_PWR1,

	TEGRA_PINGROUP_LCD_PWR2,

	TEGRA_PINGROUP_LCD_SDIN,

	TEGRA_PINGROUP_LCD_SDOUT,

	TEGRA_PINGROUP_LCD_WR_N,

	TEGRA_PINGROUP_LCD_CS0_N,

	TEGRA_PINGROUP_LCD_DC0,

	TEGRA_PINGROUP_LCD_SCK,

	TEGRA_PINGROUP_LCD_PWR0,

	TEGRA_PINGROUP_LCD_PCLK,

	TEGRA_PINGROUP_LCD_DE,

	TEGRA_PINGROUP_LCD_HSYNC,

	TEGRA_PINGROUP_LCD_VSYNC,

	TEGRA_PINGROUP_LCD_D0,

	TEGRA_PINGROUP_LCD_D1,

	TEGRA_PINGROUP_LCD_D2,

	TEGRA_PINGROUP_LCD_D3,

	TEGRA_PINGROUP_LCD_D4,

	TEGRA_PINGROUP_LCD_D5,

	TEGRA_PINGROUP_LCD_D6,

	TEGRA_PINGROUP_LCD_D7,

	TEGRA_PINGROUP_LCD_D8,

	TEGRA_PINGROUP_LCD_D9,

	TEGRA_PINGROUP_LCD_D10,

	TEGRA_PINGROUP_LCD_D11,

	TEGRA_PINGROUP_LCD_D12,

	TEGRA_PINGROUP_LCD_D13,

	TEGRA_PINGROUP_LCD_D14,

	TEGRA_PINGROUP_LCD_D15,

	TEGRA_PINGROUP_LCD_D16,

	TEGRA_PINGROUP_LCD_D17,

	TEGRA_PINGROUP_LCD_D18,

	TEGRA_PINGROUP_LCD_D19,

	TEGRA_PINGROUP_LCD_D20,

	TEGRA_PINGROUP_LCD_D21,

	TEGRA_PINGROUP_LCD_D22,

	TEGRA_PINGROUP_LCD_D23,

	TEGRA_PINGROUP_LCD_CS1_N,

	TEGRA_PINGROUP_LCD_M1,

	TEGRA_PINGROUP_LCD_DC1,

	TEGRA_PINGROUP_HDMI_INT,

	TEGRA_PINGROUP_DDC_SCL,

	TEGRA_PINGROUP_DDC_SDA,

	TEGRA_PINGROUP_CRT_HSYNC,

	TEGRA_PINGROUP_CRT_VSYNC,

	TEGRA_PINGROUP_VI_D0,

	TEGRA_PINGROUP_VI_D1,

	TEGRA_PINGROUP_VI_D2,

	TEGRA_PINGROUP_VI_D3,

	TEGRA_PINGROUP_VI_D4,

	TEGRA_PINGROUP_VI_D5,

	TEGRA_PINGROUP_VI_D6,

	TEGRA_PINGROUP_VI_D7,

	TEGRA_PINGROUP_VI_D8,

	TEGRA_PINGROUP_VI_D9,

	TEGRA_PINGROUP_VI_D10,

	TEGRA_PINGROUP_VI_D11,

	TEGRA_PINGROUP_VI_PCLK,

	TEGRA_PINGROUP_VI_MCLK,

	TEGRA_PINGROUP_VI_VSYNC,

	TEGRA_PINGROUP_VI_HSYNC,

	TEGRA_PINGROUP_UART2_RXD,

	TEGRA_PINGROUP_UART2_TXD,

	TEGRA_PINGROUP_UART2_RTS_N,

	TEGRA_PINGROUP_UART2_CTS_N,

	TEGRA_PINGROUP_UART3_TXD,

	TEGRA_PINGROUP_UART3_RXD,

	TEGRA_PINGROUP_UART3_CTS_N,

	TEGRA_PINGROUP_UART3_RTS_N,

	TEGRA_PINGROUP_GPIO_PU0,

	TEGRA_PINGROUP_GPIO_PU1,

	TEGRA_PINGROUP_GPIO_PU2,

	TEGRA_PINGROUP_GPIO_PU3,

	TEGRA_PINGROUP_GPIO_PU4,

	TEGRA_PINGROUP_GPIO_PU5,

	TEGRA_PINGROUP_GPIO_PU6,

	TEGRA_PINGROUP_GEN1_I2C_SDA,

	TEGRA_PINGROUP_GEN1_I2C_SCL,

	TEGRA_PINGROUP_DAP4_FS,

	TEGRA_PINGROUP_DAP4_DIN,

	TEGRA_PINGROUP_DAP4_DOUT,

	TEGRA_PINGROUP_DAP4_SCLK,

	TEGRA_PINGROUP_CLK3_OUT,

	TEGRA_PINGROUP_CLK3_REQ,

	TEGRA_PINGROUP_GMI_WP_N,

	TEGRA_PINGROUP_GMI_IORDY,

	TEGRA_PINGROUP_GMI_WAIT,

	TEGRA_PINGROUP_GMI_ADV_N,

	TEGRA_PINGROUP_GMI_CLK,

	TEGRA_PINGROUP_GMI_CS0_N,

	TEGRA_PINGROUP_GMI_CS1_N,

	TEGRA_PINGROUP_GMI_CS2_N,

	TEGRA_PINGROUP_GMI_CS3_N,

	TEGRA_PINGROUP_GMI_CS4_N,

	TEGRA_PINGROUP_GMI_CS6_N,

	TEGRA_PINGROUP_GMI_CS7_N,

	TEGRA_PINGROUP_GMI_AD0,

	TEGRA_PINGROUP_GMI_AD1,

	TEGRA_PINGROUP_GMI_AD2,

	TEGRA_PINGROUP_GMI_AD3,

	TEGRA_PINGROUP_GMI_AD4,

	TEGRA_PINGROUP_GMI_AD5,

	TEGRA_PINGROUP_GMI_AD6,

	TEGRA_PINGROUP_GMI_AD7,

	TEGRA_PINGROUP_GMI_AD8,

	TEGRA_PINGROUP_GMI_AD9,

	TEGRA_PINGROUP_GMI_AD10,

	TEGRA_PINGROUP_GMI_AD11,

	TEGRA_PINGROUP_GMI_AD12,

	TEGRA_PINGROUP_GMI_AD13,

	TEGRA_PINGROUP_GMI_AD14,

	TEGRA_PINGROUP_GMI_AD15,

	TEGRA_PINGROUP_GMI_A16,

	TEGRA_PINGROUP_GMI_A17,

	TEGRA_PINGROUP_GMI_A18,

	TEGRA_PINGROUP_GMI_A19,

	TEGRA_PINGROUP_GMI_WR_N,

	TEGRA_PINGROUP_GMI_OE_N,

	TEGRA_PINGROUP_GMI_DQS,

	TEGRA_PINGROUP_GMI_RST_N,

	TEGRA_PINGROUP_GEN2_I2C_SCL,

	TEGRA_PINGROUP_GEN2_I2C_SDA,

	TEGRA_PINGROUP_SDMMC4_CLK,

	TEGRA_PINGROUP_SDMMC4_CMD,

	TEGRA_PINGROUP_SDMMC4_DAT0,

	TEGRA_PINGROUP_SDMMC4_DAT1,

	TEGRA_PINGROUP_SDMMC4_DAT2,

	TEGRA_PINGROUP_SDMMC4_DAT3,

	TEGRA_PINGROUP_SDMMC4_DAT4,

	TEGRA_PINGROUP_SDMMC4_DAT5,

	TEGRA_PINGROUP_SDMMC4_DAT6,

	TEGRA_PINGROUP_SDMMC4_DAT7,

	TEGRA_PINGROUP_SDMMC4_RST_N,

	TEGRA_PINGROUP_CAM_MCLK,

	TEGRA_PINGROUP_GPIO_PCC1,

	TEGRA_PINGROUP_GPIO_PBB0,

	TEGRA_PINGROUP_CAM_I2C_SCL,

	TEGRA_PINGROUP_CAM_I2C_SDA,

	TEGRA_PINGROUP_GPIO_PBB3,

	TEGRA_PINGROUP_GPIO_PBB4,

	TEGRA_PINGROUP_GPIO_PBB5,

	TEGRA_PINGROUP_GPIO_PBB6,

	TEGRA_PINGROUP_GPIO_PBB7,

	TEGRA_PINGROUP_GPIO_PCC2,

	TEGRA_PINGROUP_JTAG_RTCK,

	TEGRA_PINGROUP_PWR_I2C_SCL,

	TEGRA_PINGROUP_PWR_I2C_SDA,

	TEGRA_PINGROUP_KB_ROW0,

	TEGRA_PINGROUP_KB_ROW1,

	TEGRA_PINGROUP_KB_ROW2,

	TEGRA_PINGROUP_KB_ROW3,

	TEGRA_PINGROUP_KB_ROW4,

	TEGRA_PINGROUP_KB_ROW5,

	TEGRA_PINGROUP_KB_ROW6,

	TEGRA_PINGROUP_KB_ROW7,

	TEGRA_PINGROUP_KB_ROW8,

	TEGRA_PINGROUP_KB_ROW9,

	TEGRA_PINGROUP_KB_ROW10,

	TEGRA_PINGROUP_KB_ROW11,

	TEGRA_PINGROUP_KB_ROW12,

	TEGRA_PINGROUP_KB_ROW13,

	TEGRA_PINGROUP_KB_ROW14,

	TEGRA_PINGROUP_KB_ROW15,

	TEGRA_PINGROUP_KB_COL0,

	TEGRA_PINGROUP_KB_COL1,

	TEGRA_PINGROUP_KB_COL2,

	TEGRA_PINGROUP_KB_COL3,

	TEGRA_PINGROUP_KB_COL4,

	TEGRA_PINGROUP_KB_COL5,

	TEGRA_PINGROUP_KB_COL6,

	TEGRA_PINGROUP_KB_COL7,

	TEGRA_PINGROUP_CLK_32K_OUT,

	TEGRA_PINGROUP_SYS_CLK_REQ,

	TEGRA_PINGROUP_CORE_PWR_REQ,

	TEGRA_PINGROUP_CPU_PWR_REQ,

	TEGRA_PINGROUP_PWR_INT_N,

	TEGRA_PINGROUP_CLK_32K_IN,

	TEGRA_PINGROUP_OWR,

	TEGRA_PINGROUP_DAP1_FS,

	TEGRA_PINGROUP_DAP1_DIN,

	TEGRA_PINGROUP_DAP1_DOUT,

	TEGRA_PINGROUP_DAP1_SCLK,

	TEGRA_PINGROUP_CLK1_REQ,

	TEGRA_PINGROUP_CLK1_OUT,

	TEGRA_PINGROUP_SPDIF_IN,

	TEGRA_PINGROUP_SPDIF_OUT,

	TEGRA_PINGROUP_DAP2_FS,

	TEGRA_PINGROUP_DAP2_DIN,

	TEGRA_PINGROUP_DAP2_DOUT,

	TEGRA_PINGROUP_DAP2_SCLK,

	TEGRA_PINGROUP_SPI2_MOSI,

	TEGRA_PINGROUP_SPI2_MISO,

	TEGRA_PINGROUP_SPI2_CS0_N,

	TEGRA_PINGROUP_SPI2_SCK,

	TEGRA_PINGROUP_SPI1_MOSI,

	TEGRA_PINGROUP_SPI1_SCK,

	TEGRA_PINGROUP_SPI1_CS0_N,

	TEGRA_PINGROUP_SPI1_MISO,

	TEGRA_PINGROUP_SPI2_CS1_N,

	TEGRA_PINGROUP_SPI2_CS2_N,

	TEGRA_PINGROUP_SDMMC3_CLK,

	TEGRA_PINGROUP_SDMMC3_CMD,

	TEGRA_PINGROUP_SDMMC3_DAT0,

	TEGRA_PINGROUP_SDMMC3_DAT1,

	TEGRA_PINGROUP_SDMMC3_DAT2,

	TEGRA_PINGROUP_SDMMC3_DAT3,

	TEGRA_PINGROUP_SDMMC3_DAT4,

	TEGRA_PINGROUP_SDMMC3_DAT5,

	TEGRA_PINGROUP_SDMMC3_DAT6,

	TEGRA_PINGROUP_SDMMC3_DAT7,

	TEGRA_PINGROUP_PEX_L0_PRSNT_N,

	TEGRA_PINGROUP_PEX_L0_RST_N,

	TEGRA_PINGROUP_PEX_L0_CLKREQ_N,

	TEGRA_PINGROUP_PEX_WAKE_N,

	TEGRA_PINGROUP_PEX_L1_PRSNT_N,

	TEGRA_PINGROUP_PEX_L1_RST_N,

	TEGRA_PINGROUP_PEX_L1_CLKREQ_N,

	TEGRA_PINGROUP_PEX_L2_PRSNT_N,

	TEGRA_PINGROUP_PEX_L2_RST_N,

	TEGRA_PINGROUP_PEX_L2_CLKREQ_N,

	TEGRA_PINGROUP_HDMI_CEC,

	TEGRA_MAX_PINGROUP,

};



enum tegra_drive_pingroup {

	TEGRA_DRIVE_PINGROUP_AO1 = 0,

	TEGRA_DRIVE_PINGROUP_AO2,

	TEGRA_DRIVE_PINGROUP_AT1,

	TEGRA_DRIVE_PINGROUP_AT2,

	TEGRA_DRIVE_PINGROUP_AT3,

	TEGRA_DRIVE_PINGROUP_AT4,

	TEGRA_DRIVE_PINGROUP_AT5,

	TEGRA_DRIVE_PINGROUP_CDEV1,

	TEGRA_DRIVE_PINGROUP_CDEV2,

	TEGRA_DRIVE_PINGROUP_CSUS,

	TEGRA_DRIVE_PINGROUP_DAP1,

	TEGRA_DRIVE_PINGROUP_DAP2,

	TEGRA_DRIVE_PINGROUP_DAP3,

	TEGRA_DRIVE_PINGROUP_DAP4,

	TEGRA_DRIVE_PINGROUP_DBG,

	TEGRA_DRIVE_PINGROUP_LCD1,

	TEGRA_DRIVE_PINGROUP_LCD2,

	TEGRA_DRIVE_PINGROUP_SDIO2,

	TEGRA_DRIVE_PINGROUP_SDIO3,

	TEGRA_DRIVE_PINGROUP_SPI,

	TEGRA_DRIVE_PINGROUP_UAA,

	TEGRA_DRIVE_PINGROUP_UAB,

	TEGRA_DRIVE_PINGROUP_UART2,

	TEGRA_DRIVE_PINGROUP_UART3,

	TEGRA_DRIVE_PINGROUP_VI1,

	TEGRA_DRIVE_PINGROUP_SDIO1,

	TEGRA_DRIVE_PINGROUP_CRT,

	TEGRA_DRIVE_PINGROUP_DDC,

	TEGRA_DRIVE_PINGROUP_GMA,

	TEGRA_DRIVE_PINGROUP_GMB,

	TEGRA_DRIVE_PINGROUP_GMC,

	TEGRA_DRIVE_PINGROUP_GMD,

	TEGRA_DRIVE_PINGROUP_GME,

	TEGRA_DRIVE_PINGROUP_GMF,

	TEGRA_DRIVE_PINGROUP_GMG,

	TEGRA_DRIVE_PINGROUP_GMH,

	TEGRA_DRIVE_PINGROUP_OWR,

	TEGRA_DRIVE_PINGROUP_UAD,

	TEGRA_DRIVE_PINGROUP_GPV,

	TEGRA_DRIVE_PINGROUP_DEV3,

	TEGRA_DRIVE_PINGROUP_CEC,

	TEGRA_MAX_DRIVE_PINGROUP,

};



#endif

arch/arm/mach-tegra/include/mach/pinmux.h

+53 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ enum tegra_mux_func { 
	TEGRA_MUX_RSVD2 = 0x8001,

	TEGRA_MUX_RSVD3 = 0x8002,

	TEGRA_MUX_RSVD4 = 0x8003,

	TEGRA_MUX_INVALID = 0x4000,

	TEGRA_MUX_NONE = -1,

	TEGRA_MUX_AHB_CLK,

	TEGRA_MUX_APB_CLK,
@@ -85,6 +86,49 @@ enum tegra_mux_func { 
	TEGRA_MUX_VI,

	TEGRA_MUX_VI_SENSOR_CLK,

	TEGRA_MUX_XIO,

	TEGRA_MUX_BLINK,

	TEGRA_MUX_CEC,

	TEGRA_MUX_CLK12,

	TEGRA_MUX_DAP,

	TEGRA_MUX_DAPSDMMC2,

	TEGRA_MUX_DDR,

	TEGRA_MUX_DEV3,

	TEGRA_MUX_DTV,

	TEGRA_MUX_VI_ALT1,

	TEGRA_MUX_VI_ALT2,

	TEGRA_MUX_VI_ALT3,

	TEGRA_MUX_EMC_DLL,

	TEGRA_MUX_EXTPERIPH1,

	TEGRA_MUX_EXTPERIPH2,

	TEGRA_MUX_EXTPERIPH3,

	TEGRA_MUX_GMI_ALT,

	TEGRA_MUX_HDA,

	TEGRA_MUX_HSI,

	TEGRA_MUX_I2C4,

	TEGRA_MUX_I2C5,

	TEGRA_MUX_I2CPWR,

	TEGRA_MUX_I2S0,

	TEGRA_MUX_I2S1,

	TEGRA_MUX_I2S2,

	TEGRA_MUX_I2S3,

	TEGRA_MUX_I2S4,

	TEGRA_MUX_NAND_ALT,

	TEGRA_MUX_POPSDIO4,

	TEGRA_MUX_POPSDMMC4,

	TEGRA_MUX_PWM0,

	TEGRA_MUX_PWM1,

	TEGRA_MUX_PWM2,

	TEGRA_MUX_PWM3,

	TEGRA_MUX_SATA,

	TEGRA_MUX_SPI5,

	TEGRA_MUX_SPI6,

	TEGRA_MUX_SYSCLK,

	TEGRA_MUX_VGP1,

	TEGRA_MUX_VGP2,

	TEGRA_MUX_VGP3,

	TEGRA_MUX_VGP4,

	TEGRA_MUX_VGP5,

	TEGRA_MUX_VGP6,

	TEGRA_MUX_SAFE,

	TEGRA_MAX_MUX,

};
@@ -115,6 +159,12 @@ enum tegra_vddio { 
	TEGRA_VDDIO_SYS,

	TEGRA_VDDIO_AUDIO,

	TEGRA_VDDIO_SD,

	TEGRA_VDDIO_CAM,

	TEGRA_VDDIO_GMI,

	TEGRA_VDDIO_PEXCTL,

	TEGRA_VDDIO_SDMMC1,

	TEGRA_VDDIO_SDMMC3,

	TEGRA_VDDIO_SDMMC4,

};



struct tegra_pingroup_config {
@@ -230,6 +280,9 @@ typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg, 
void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,

	const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);



void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,

	const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);



int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);

int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);

arch/arm/mach-tegra/pinmux-tegra30-tables.c

0 → 100644
+376 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-tegra/pinmux.c

+48 −0
Original line number Diff line number Diff line
@@ -100,6 +100,49 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = { 
	[TEGRA_MUX_VI] = "VI",

	[TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",

	[TEGRA_MUX_XIO] = "XIO",

	[TEGRA_MUX_BLINK] = "BLINK",

	[TEGRA_MUX_CEC] = "CEC",

	[TEGRA_MUX_CLK12] = "CLK12",

	[TEGRA_MUX_DAP] = "DAP",

	[TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",

	[TEGRA_MUX_DDR] = "DDR",

	[TEGRA_MUX_DEV3] = "DEV3",

	[TEGRA_MUX_DTV] = "DTV",

	[TEGRA_MUX_VI_ALT1] = "VI_ALT1",

	[TEGRA_MUX_VI_ALT2] = "VI_ALT2",

	[TEGRA_MUX_VI_ALT3] = "VI_ALT3",

	[TEGRA_MUX_EMC_DLL] = "EMC_DLL",

	[TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",

	[TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",

	[TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",

	[TEGRA_MUX_GMI_ALT] = "GMI_ALT",

	[TEGRA_MUX_HDA] = "HDA",

	[TEGRA_MUX_HSI] = "HSI",

	[TEGRA_MUX_I2C4] = "I2C4",

	[TEGRA_MUX_I2C5] = "I2C5",

	[TEGRA_MUX_I2CPWR] = "I2CPWR",

	[TEGRA_MUX_I2S0] = "I2S0",

	[TEGRA_MUX_I2S1] = "I2S1",

	[TEGRA_MUX_I2S2] = "I2S2",

	[TEGRA_MUX_I2S3] = "I2S3",

	[TEGRA_MUX_I2S4] = "I2S4",

	[TEGRA_MUX_NAND_ALT] = "NAND_ALT",

	[TEGRA_MUX_POPSDIO4] = "POPSDIO4",

	[TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",

	[TEGRA_MUX_PWM0] = "PWM0",

	[TEGRA_MUX_PWM1] = "PWM2",

	[TEGRA_MUX_PWM2] = "PWM2",

	[TEGRA_MUX_PWM3] = "PWM3",

	[TEGRA_MUX_SATA] = "SATA",

	[TEGRA_MUX_SPI5] = "SPI5",

	[TEGRA_MUX_SPI6] = "SPI6",

	[TEGRA_MUX_SYSCLK] = "SYSCLK",

	[TEGRA_MUX_VGP1] = "VGP1",

	[TEGRA_MUX_VGP2] = "VGP2",

	[TEGRA_MUX_VGP3] = "VGP3",

	[TEGRA_MUX_VGP4] = "VGP4",

	[TEGRA_MUX_VGP5] = "VGP5",

	[TEGRA_MUX_VGP6] = "VGP6",

	[TEGRA_MUX_SAFE] = "<safe>",

};
@@ -667,7 +710,12 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co 
}



static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {

#ifdef CONFIG_ARCH_TEGRA_2x_SOC

	{ .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },

#endif

#ifdef CONFIG_ARCH_TEGRA_3x_SOC

	{ .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },

#endif

	{ },

};