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Commit 2403a874 authored by Neeraj Upadhyay's avatar Neeraj Upadhyay Committed by Gerrit - the friendly Code Review server
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arm64: Add BTAC/LinkStack sanitizations for Kryo 



Kryo cores are exposed to two vulnerabilities due to subroutine
return (called LINK-STACK) and branch target predictors.
These two issues can be mitigated through software workarounds.

Kernel:
 - Apply LINK-STACK mitigation which is issue 16 nested BL instructions
   on process context switch 'cpu_do_switch_mm()' where ASID changes.
 - Apply psci based branch predictor invalidation.

Change-Id: I983a12dabcd45e3ec757732a44fc567c12228d8b
Signed-off-by: default avatarNeeraj Upadhyay <neeraju@codeaurora.org>
parent 115d0767

arch/arm64/kernel/cpu_errata.c

+23 −1
Original line number Diff line number Diff line
@@ -147,7 +147,7 @@ static void enable_psci_bp_hardening(void *data) 


}



static void __maybe_unused qcom_link_stack_sanitization(void)

static void qcom_link_stack_sanitization(void)

{

	u64 tmp;
@@ -159,6 +159,22 @@ static void __maybe_unused qcom_link_stack_sanitization(void) 
		     : "=&r" (tmp));

}



static void qcom_bp_hardening(void)

{

	qcom_link_stack_sanitization();

	if (psci_ops.get_version)

		psci_ops.get_version();

}



static void enable_qcom_bp_hardening(void *data)

{

	const struct arm64_cpu_capabilities *entry = data;



	install_bp_hardening_cb(entry,

				(bp_hardening_cb_t)qcom_bp_hardening,

				 __psci_hyp_bp_inval_start,

				 __psci_hyp_bp_inval_end);

}

#endif	/* CONFIG_HARDEN_BRANCH_PREDICTOR */



#define MIDR_RANGE(model, min, max) \
@@ -221,6 +237,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

		.enable = enable_psci_bp_hardening,

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		.midr_model = MIDR_QCOM_KRYO,

		.matches = is_kryo_midr,

		.enable = enable_qcom_bp_hardening,

	},

#endif

	{

	}