Merge tag 'marvell-mvneta-fix-and-clk-support-3.8' of...

  property, a single integer).

- phy-mode: The interface between the SoC and the PHY (a string that

  of_get_phy_mode() can understand)

- clock-frequency: frequency of the peripheral clock of the SoC.

- clocks: a pointer to the reference clock for this device.

Example:

	compatible = "marvell,armada-370-neta";

	reg = <0xd0070000 0x2500>;

	interrupts = <8>;

	clock-frequency = <250000000>;

	clocks = <&gate_clk 4>;

	status = "okay";

	phy = <&phy0>;

	phy-mode = "rgmii-id";

#include <linux/of_net.h>

#include <linux/of_address.h>

#include <linux/phy.h>

#include <linux/clk.h>

/* Registers */

#define MVNETA_RXQ_CONFIG_REG(q)                (0x1400 + ((q) << 2))

	int weight;

	/* Core clock */

	unsigned int clk_rate_hz;

	struct clk *clk;

	u8 mcast_count[256];

	u16 tx_ring_size;

	u16 rx_ring_size;

static void mvneta_rx_time_coal_set(struct mvneta_port *pp,

				    struct mvneta_rx_queue *rxq, u32 value)

{

	u32 val = (pp->clk_rate_hz / 1000000) * value;

	u32 val;

	unsigned long clk_rate;

	clk_rate = clk_get_rate(pp->clk);

	val = (clk_rate / 1000000) * value;

	mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);

	rxq->time_coal = value;

	return 0;

}

static void __devexit mvneta_deinit(struct mvneta_port *pp)

static void mvneta_deinit(struct mvneta_port *pp)

{

	kfree(pp->txqs);

	kfree(pp->rxqs);

	const struct mbus_dram_target_info *dram_target_info;

	struct device_node *dn = pdev->dev.of_node;

	struct device_node *phy_node;

	u32 phy_addr, clk_rate_hz;

	u32 phy_addr;

	struct mvneta_port *pp;

	struct net_device *dev;

	const char *mac_addr;

		goto err_free_irq;

	}

	if (of_property_read_u32(dn, "clock-frequency", &clk_rate_hz) != 0) {

		dev_err(&pdev->dev, "could not read clock-frequency\n");

		err = -EINVAL;

		goto err_free_irq;

	}

	mac_addr = of_get_mac_address(dn);

	if (!mac_addr || !is_valid_ether_addr(mac_addr))

	clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);

	pp->weight = MVNETA_RX_POLL_WEIGHT;

	pp->clk_rate_hz = clk_rate_hz;

	pp->phy_node = phy_node;

	pp->phy_interface = phy_mode;

		goto err_free_irq;

	}

	pp->clk = devm_clk_get(&pdev->dev, NULL);

	if (IS_ERR(pp->clk)) {

		err = PTR_ERR(pp->clk);

		goto err_unmap;

	}

	clk_prepare_enable(pp->clk);

	pp->tx_done_timer.data = (unsigned long)dev;

	pp->tx_ring_size = MVNETA_MAX_TXD;

	err = mvneta_init(pp, phy_addr);

	if (err < 0) {

		dev_err(&pdev->dev, "can't init eth hal\n");

		goto err_unmap;

		goto err_clk;

	}

	mvneta_port_power_up(pp, phy_mode);

err_deinit:

	mvneta_deinit(pp);

err_clk:

	clk_disable_unprepare(pp->clk);

err_unmap:

	iounmap(pp->base);

err_free_irq:

	unregister_netdev(dev);

	mvneta_deinit(pp);

	clk_disable_unprepare(pp->clk);

	iounmap(pp->base);

	irq_dispose_mapping(dev->irq);

	free_netdev(dev);