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Commit 23f09ce3 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/overlay: Make the overlay control struct opaque. 



Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5dcdbcb0

drivers/gpu/drm/i915/intel_display.c

+4 −4
Original line number Diff line number Diff line
@@ -2224,11 +2224,11 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) 
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)

{

	if (!enable && intel_crtc->overlay) {

		struct intel_overlay *overlay = intel_crtc->overlay;

		struct drm_device *dev = intel_crtc->base.dev;



		mutex_lock(&overlay->dev->struct_mutex);

		(void) intel_overlay_switch_off(overlay, false);

		mutex_unlock(&overlay->dev->struct_mutex);

		mutex_lock(&dev->struct_mutex);

		(void) intel_overlay_switch_off(intel_crtc->overlay, false);

		mutex_unlock(&dev->struct_mutex);

	}



	/* Let userspace switch the overlay on again. In most cases userspace

drivers/gpu/drm/i915/intel_drv.h

+0 −24
Original line number Diff line number Diff line
@@ -146,30 +146,6 @@ struct intel_connector { 
	struct drm_connector base;

};



struct intel_crtc;

struct intel_overlay {

	struct drm_device *dev;

	struct intel_crtc *crtc;

	struct drm_i915_gem_object *vid_bo;

	struct drm_i915_gem_object *old_vid_bo;

	int active;

	int pfit_active;

	u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */

	u32 color_key;

	u32 brightness, contrast, saturation;

	u32 old_xscale, old_yscale;

	/* register access */

	u32 flip_addr;

	struct drm_i915_gem_object *reg_bo;

	/* flip handling */

	uint32_t last_flip_req;

	int hw_wedged;

#define HW_WEDGED		1

#define NEEDS_WAIT_FOR_FLIP	2

#define RELEASE_OLD_VID		3

#define SWITCH_OFF		4

};



struct intel_crtc {

	struct drm_crtc base;

	enum pipe pipe;

drivers/gpu/drm/i915/intel_overlay.c

+23 −0
Original line number Diff line number Diff line
@@ -170,6 +170,29 @@ struct overlay_registers { 
    u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];

};



struct intel_overlay {

	struct drm_device *dev;

	struct intel_crtc *crtc;

	struct drm_i915_gem_object *vid_bo;

	struct drm_i915_gem_object *old_vid_bo;

	int active;

	int pfit_active;

	u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */

	u32 color_key;

	u32 brightness, contrast, saturation;

	u32 old_xscale, old_yscale;

	/* register access */

	u32 flip_addr;

	struct drm_i915_gem_object *reg_bo;

	/* flip handling */

	uint32_t last_flip_req;

	int hw_wedged;

#define HW_WEDGED		1

#define NEEDS_WAIT_FOR_FLIP	2

#define RELEASE_OLD_VID		3

#define SWITCH_OFF		4

};



static struct overlay_registers *

intel_overlay_map_regs_atomic(struct intel_overlay *overlay,

			      int slot)