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Commit 22b03aea authored by Sandeep Panda's avatar Sandeep Panda
Browse files

clk: qcom: mdss: add support for msmtitanium DSI PLL 



Add support for DSI PLL on msmtitanium platform, which is
needed to driver DSI pixel and byte clocks.

Change-Id: Ibcd5e0d01ea23f86c020119123016f011f23b6d0
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
parent bd4743e8

Documentation/devicetree/bindings/fb/mdss-pll.txt

+2 −1
Original line number Diff line number Diff line
@@ -14,7 +14,8 @@ Required properties: 
			"qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",

			"qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",

			"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_dsi_pll_8952",

			"qcom,mdss_dsi_pll_8937", "qcom,mdss_hdmi_pll_8996_v3_1p8"

			"qcom,mdss_dsi_pll_8937", "qcom,mdss_hdmi_pll_8996_v3_1p8",

			"qcom,mdss_dsi_pll_titanium"

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

drivers/clk/msm/mdss/mdss-dsi-pll-8996.c

+8 −2
Original line number Diff line number Diff line
@@ -526,9 +526,12 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev, 
		dsi1pll_shadow_vco_clk.priv = pll_res;



		pll_res->vco_delay = VCO_DELAY_USEC;

		if ((pll_res->target_id == MDSS_PLL_TARGET_8996) ||

			(pll_res->target_id == MDSS_PLL_TARGET_TITANIUM)) {

			rc = of_msm_clock_register(pdev->dev.of_node,

				mdss_dsi_pllcc_8996_1,

				ARRAY_SIZE(mdss_dsi_pllcc_8996_1));

		}

	} else {

		dsi0pll_byte_clk_src.priv = pll_res;

		dsi0pll_pixel_clk_src.priv = pll_res;
@@ -543,10 +546,13 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev, 
		dsi0pll_shadow_vco_clk.priv = pll_res;



		pll_res->vco_delay = VCO_DELAY_USEC;

		if ((pll_res->target_id == MDSS_PLL_TARGET_8996) ||

			(pll_res->target_id == MDSS_PLL_TARGET_TITANIUM)) {

			rc = of_msm_clock_register(pdev->dev.of_node,

				mdss_dsi_pllcc_8996,

				ARRAY_SIZE(mdss_dsi_pllcc_8996));

		}

	}



	if (!rc) {

		pr_info("Registered DSI PLL ndx=%d clocks successfully\n",

drivers/clk/msm/mdss/mdss-pll.c

+5 −0
Original line number Diff line number Diff line
@@ -140,6 +140,10 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, 
		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;

		pll_res->target_id = MDSS_PLL_TARGET_8996;

		pll_res->revision = 2;

	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_titanium")) {

		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;

		pll_res->target_id = MDSS_PLL_TARGET_TITANIUM;

		pll_res->revision = 2;

	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) {

		pll_res->pll_interface_type = MDSS_HDMI_PLL_8996;

	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v2")) {
@@ -383,6 +387,7 @@ static const struct of_device_id mdss_pll_dt_match[] = { 
	{.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"},

	{.compatible = "qcom,mdss_dsi_pll_8952"},

	{.compatible = "qcom,mdss_dsi_pll_8937"},

	{.compatible = "qcom,mdss_dsi_pll_titanium"},

	{}

};

drivers/clk/msm/mdss/mdss-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ enum { 
	MDSS_PLL_TARGET_8996,

	MDSS_PLL_TARGET_8952,

	MDSS_PLL_TARGET_8937,

	MDSS_PLL_TARGET_TITANIUM,

};



#define DFPS_MAX_NUM_OF_FRAME_RATES 10