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Commit 22ae77bc authored by Linus Torvalds's avatar Linus Torvalds
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* git://git.infradead.org/mtd-2.6: (53 commits)
  [MTD] struct device - replace bus_id with dev_name(), dev_set_name()
  [MTD] [NOR] Fixup for Numonyx M29W128 chips
  [MTD] mtdpart: Make ecc_stats more realistic.
  powerpc/85xx: TQM8548: Update DTS file for multi-chip support
  powerpc: NAND: FSL UPM: document new bindings
  [MTD] [NAND] FSL-UPM: Add wait flags to support board/chip specific delays
  [MTD] [NAND] FSL-UPM: add multi chip support
  [MTD] [NOR] Add device parent info to physmap_of
  [MTD] [NAND] Add support for NAND on the Socrates board
  [MTD] [NAND] Add support for 4KiB pages.
  [MTD] sysfs support should not depend on CONFIG_PROC_FS
  [MTD] [NAND] Add parent info for CAFÉ controller
  [MTD] support driver model updates
  [MTD] driver model updates (part 2)
  [MTD] driver model updates
  [MTD] [NAND] move gen_nand's probe function to .devinit.text
  [MTD] [MAPS] move sa1100 flash's probe function to .devinit.text
  [MTD] fix use after free in register_mtd_blktrans
  [MTD] [MAPS] Drop now unused sharpsl-flash map
  [MTD] ofpart: Check name property to determine partition nodes.
  ...

Manually fix trivial conflict in drivers/mtd/maps/Makefile
parents e379ec7c 30bbf140
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+37 −2
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@@ -5,9 +5,21 @@ Required properties:
- reg : should specify localbus chip select and size used for the chip.
- fsl,upm-addr-offset : UPM pattern offset for the address latch.
- fsl,upm-cmd-offset : UPM pattern offset for the command latch.
- gpios : may specify optional GPIO connected to the Ready-Not-Busy pin.

Example:
Optional properties:
- fsl,upm-wait-flags : add chip-dependent short delays after running the
	UPM pattern (0x1), after writing a data byte (0x2) or after
	writing out a buffer (0x4).
- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
	The corresponding address lines are used to select the chip.
- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
	(R/B#). For multi-chip devices, "n" GPIO definitions are required
	according to the number of chips.
- chip-delay : chip dependent delay for transfering data from array to
	read registers (tR). Required if property "gpios" is not used
	(R/B# pins not connected).

Examples:

upm@1,0 {
	compatible = "fsl,upm-nand";
@@ -26,3 +38,26 @@ upm@1,0 {
		};
	};
};

upm@3,0 {
	#address-cells = <0>;
	#size-cells = <0>;
	compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
	reg = <3 0x0 0x800>;
	fsl,upm-addr-offset = <0x10>;
	fsl,upm-cmd-offset = <0x08>;
	/* Multi-chip NAND device */
	fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
	fsl,upm-wait-flags = <0x5>;
	chip-delay = <25>; // in micro-seconds

	nand@0 {
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			    label = "fs";
			    reg = <0x00000000 0x10000000>;
		};
	};
};
+80 −0
Original line number Diff line number Diff line
/*
 * mach-davinci/nand.h
 *
 * Copyright © 2006 Texas Instruments.
 *
 * Ported to 2.6.23 Copyright © 2008 by
 *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
 *   Troy Kisky <troy.kisky@boundarydevices.com>
 *   Dirk Behme <Dirk.Behme@gmail.com>
 *
 * --------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __ARCH_ARM_DAVINCI_NAND_H
#define __ARCH_ARM_DAVINCI_NAND_H

#include <linux/mtd/nand.h>

#define NRCSR_OFFSET		0x00
#define AWCCR_OFFSET		0x04
#define A1CR_OFFSET		0x10
#define NANDFCR_OFFSET		0x60
#define NANDFSR_OFFSET		0x64
#define NANDF1ECC_OFFSET	0x70

/* 4-bit ECC syndrome registers */
#define NAND_4BIT_ECC_LOAD_OFFSET	0xbc
#define NAND_4BIT_ECC1_OFFSET		0xc0
#define NAND_4BIT_ECC2_OFFSET		0xc4
#define NAND_4BIT_ECC3_OFFSET		0xc8
#define NAND_4BIT_ECC4_OFFSET		0xcc
#define NAND_ERR_ADD1_OFFSET		0xd0
#define NAND_ERR_ADD2_OFFSET		0xd4
#define NAND_ERR_ERRVAL1_OFFSET		0xd8
#define NAND_ERR_ERRVAL2_OFFSET		0xdc

/* NOTE:  boards don't need to use these address bits
 * for ALE/CLE unless they support booting from NAND.
 * They're used unless platform data overrides them.
 */
#define	MASK_ALE		0x08
#define	MASK_CLE		0x10

struct davinci_nand_pdata {		/* platform_data */
	uint32_t		mask_ale;
	uint32_t		mask_cle;

	/* for packages using two chipselects */
	uint32_t		mask_chipsel;

	/* board's default static partition info */
	struct mtd_partition	*parts;
	unsigned		nr_parts;

	/* none  == NAND_ECC_NONE (strongly *not* advised!!)
	 * soft  == NAND_ECC_SOFT
	 * 1-bit == NAND_ECC_HW
	 * 4-bit == NAND_ECC_HW_SYNDROME (not on all chips)
	 */
	nand_ecc_modes_t	ecc_mode;

	/* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */
	unsigned		options;
};

#endif	/* __ARCH_ARM_DAVINCI_NAND_H */
+3 −0
Original line number Diff line number Diff line
@@ -49,6 +49,9 @@ struct pxa3xx_nand_platform_data {
	 */
	int	enable_arbiter;

	/* allow platform code to keep OBM/bootloader defined NFC config */
	int	keep_config;

	const struct mtd_partition		*parts;
	unsigned int				nr_parts;

+1 −1
Original line number Diff line number Diff line
@@ -337,7 +337,7 @@ int _access_ok(unsigned long addr, unsigned long size)
	if (addr >= memory_mtd_end && (addr + size) <= physical_mem_end)
		return 1;

#ifdef CONFIG_ROMFS_MTD_FS
#ifdef CONFIG_ROMFS_ON_MTD
	/* For XIP, allow user space to use pointers within the ROMFS.  */
	if (addr >= memory_mtd_start && (addr + size) <= memory_mtd_end)
		return 1;
+30 −0
Original line number Diff line number Diff line
/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * (C) Copyright TOSHIBA CORPORATION 2007
 */
#ifndef __ASM_TXX9_NDFMC_H
#define __ASM_TXX9_NDFMC_H

#define NDFMC_PLAT_FLAG_USE_BSPRT	0x01
#define NDFMC_PLAT_FLAG_NO_RSTR		0x02
#define NDFMC_PLAT_FLAG_HOLDADD		0x04
#define NDFMC_PLAT_FLAG_DUMMYWRITE	0x08

struct txx9ndfmc_platform_data {
	unsigned int shift;
	unsigned int gbus_clock;
	unsigned int hold;		/* hold time in nanosecond */
	unsigned int spw;		/* strobe pulse width in nanosecond */
	unsigned int flags;
	unsigned char ch_mask;		/* available channel bitmask */
	unsigned char wp_mask;		/* write-protect bitmask */
	unsigned char wide_mask;	/* 16bit-nand bitmask */
};

void txx9_ndfmc_init(unsigned long baseaddr,
		     const struct txx9ndfmc_platform_data *plat_data);

#endif /* __ASM_TXX9_NDFMC_H */
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