drm/nvc0/fifo: mask unhandled intr bits when seen, rather than all intrs (22a7a27b) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -594,9 +594,9 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev)
		}

		if (stat) {
		nv_fatal(priv, "unhandled status 0x%08x\n", stat);
		nv_error(priv, "INTR 0x%08x\n", stat);
		nv_mask(priv, 0x002140, stat, 0x00000000);
		nv_wr32(priv, 0x002100, stat);
		nv_wr32(priv, 0x002140, 0);
		}
		}