Loading arch/mips/include/asm/gic.h +10 −10 Original line number Diff line number Diff line Loading @@ -38,8 +38,8 @@ (_gic_base + segment##_##SECTION_OFS + offset) #ifdef GICISBYTELITTLEENDIAN #define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data) #define GICWRITE(reg, data) (reg) = cpu_to_le32(data) #define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data)) #define GICWRITE(reg, data) ((reg) = cpu_to_le32(data)) #define GICBIS(reg, bits) \ ({unsigned int data; \ GICREAD(reg, data); \ Loading @@ -48,9 +48,9 @@ }) #else #define GICREAD(reg, data) (data) = (reg) #define GICWRITE(reg, data) (reg) = (data) #define GICBIS(reg, bits) (reg) |= (bits) #define GICREAD(reg, data) ((data) = (reg)) #define GICWRITE(reg, data) ((reg) = (data)) #define GICBIS(reg, bits) ((reg) |= (bits)) #endif Loading arch/mips/kernel/irq-gic.c +16 −24 Original line number Diff line number Diff line #undef DEBUG /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include <linux/bitmap.h> #include <linux/init.h> #include <linux/smp.h> Loading @@ -11,7 +17,6 @@ #include <linux/hardirq.h> #include <asm-generic/bitops/find.h> unsigned long _gic_base; unsigned int gic_irq_base; unsigned int gic_irq_flags[GIC_NUM_INTRS]; Loading @@ -22,17 +27,15 @@ static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; void gic_send_ipi(unsigned int intr) { pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, read_c0_status()); GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); } /* This is Malta specific and needs to be exported */ static void __init vpe_local_setup(unsigned int numvpes) { int i; unsigned long timer_interrupt = 5, perf_interrupt = 5; unsigned long timer_interrupt = GIC_INT_TMR; unsigned long perf_interrupt = GIC_INT_PERFCTR; unsigned int vpe_ctl; int i; /* * Setup the default performance counter timer interrupts Loading Loading @@ -79,40 +82,30 @@ unsigned int gic_get_int(void) bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS); bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS); i = find_first_bit(pending, GIC_NUM_INTRS); pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i); return i; return find_first_bit(pending, GIC_NUM_INTRS); } static void gic_mask_irq(struct irq_data *d) { unsigned int irq = d->irq - gic_irq_base; pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); GIC_CLR_INTR_MASK(irq); GIC_CLR_INTR_MASK(d->irq - gic_irq_base); } static void gic_unmask_irq(struct irq_data *d) { unsigned int irq = d->irq - gic_irq_base; pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); GIC_SET_INTR_MASK(irq); GIC_SET_INTR_MASK(d->irq - gic_irq_base); } #ifdef CONFIG_SMP static DEFINE_SPINLOCK(gic_lock); static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) { unsigned int irq = d->irq - gic_irq_base; unsigned int irq = (d->irq - gic_irq_base); cpumask_t tmp = CPU_MASK_NONE; unsigned long flags; int i; pr_debug("%s(%d) called\n", __func__, irq); cpumask_and(&tmp, cpumask, cpu_online_mask); if (cpus_empty(tmp)) return -1; Loading Loading @@ -176,6 +169,7 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, /* Init Intr Masks */ GIC_CLR_INTR_MASK(intr); /* Initialise per-cpu Interrupt software masks */ if (flags & GIC_FLAG_IPI) set_bit(intr, pcpu_masks[cpu].pcpu_mask); Loading Loading @@ -237,8 +231,6 @@ void __init gic_init(unsigned long gic_base_addr, numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> GIC_SH_CONFIG_NUMVPES_SHF; pr_debug("%s called\n", __func__); gic_basic_init(numintrs, numvpes, intr_map, intr_map_size); gic_platform_init(numintrs, &gic_irq_controller); Loading Loading
arch/mips/include/asm/gic.h +10 −10 Original line number Diff line number Diff line Loading @@ -38,8 +38,8 @@ (_gic_base + segment##_##SECTION_OFS + offset) #ifdef GICISBYTELITTLEENDIAN #define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data) #define GICWRITE(reg, data) (reg) = cpu_to_le32(data) #define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data)) #define GICWRITE(reg, data) ((reg) = cpu_to_le32(data)) #define GICBIS(reg, bits) \ ({unsigned int data; \ GICREAD(reg, data); \ Loading @@ -48,9 +48,9 @@ }) #else #define GICREAD(reg, data) (data) = (reg) #define GICWRITE(reg, data) (reg) = (data) #define GICBIS(reg, bits) (reg) |= (bits) #define GICREAD(reg, data) ((data) = (reg)) #define GICWRITE(reg, data) ((reg) = (data)) #define GICBIS(reg, bits) ((reg) |= (bits)) #endif Loading
arch/mips/kernel/irq-gic.c +16 −24 Original line number Diff line number Diff line #undef DEBUG /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. */ #include <linux/bitmap.h> #include <linux/init.h> #include <linux/smp.h> Loading @@ -11,7 +17,6 @@ #include <linux/hardirq.h> #include <asm-generic/bitops/find.h> unsigned long _gic_base; unsigned int gic_irq_base; unsigned int gic_irq_flags[GIC_NUM_INTRS]; Loading @@ -22,17 +27,15 @@ static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; void gic_send_ipi(unsigned int intr) { pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, read_c0_status()); GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); } /* This is Malta specific and needs to be exported */ static void __init vpe_local_setup(unsigned int numvpes) { int i; unsigned long timer_interrupt = 5, perf_interrupt = 5; unsigned long timer_interrupt = GIC_INT_TMR; unsigned long perf_interrupt = GIC_INT_PERFCTR; unsigned int vpe_ctl; int i; /* * Setup the default performance counter timer interrupts Loading Loading @@ -79,40 +82,30 @@ unsigned int gic_get_int(void) bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS); bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS); i = find_first_bit(pending, GIC_NUM_INTRS); pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i); return i; return find_first_bit(pending, GIC_NUM_INTRS); } static void gic_mask_irq(struct irq_data *d) { unsigned int irq = d->irq - gic_irq_base; pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); GIC_CLR_INTR_MASK(irq); GIC_CLR_INTR_MASK(d->irq - gic_irq_base); } static void gic_unmask_irq(struct irq_data *d) { unsigned int irq = d->irq - gic_irq_base; pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); GIC_SET_INTR_MASK(irq); GIC_SET_INTR_MASK(d->irq - gic_irq_base); } #ifdef CONFIG_SMP static DEFINE_SPINLOCK(gic_lock); static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) { unsigned int irq = d->irq - gic_irq_base; unsigned int irq = (d->irq - gic_irq_base); cpumask_t tmp = CPU_MASK_NONE; unsigned long flags; int i; pr_debug("%s(%d) called\n", __func__, irq); cpumask_and(&tmp, cpumask, cpu_online_mask); if (cpus_empty(tmp)) return -1; Loading Loading @@ -176,6 +169,7 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, /* Init Intr Masks */ GIC_CLR_INTR_MASK(intr); /* Initialise per-cpu Interrupt software masks */ if (flags & GIC_FLAG_IPI) set_bit(intr, pcpu_masks[cpu].pcpu_mask); Loading Loading @@ -237,8 +231,6 @@ void __init gic_init(unsigned long gic_base_addr, numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> GIC_SH_CONFIG_NUMVPES_SHF; pr_debug("%s called\n", __func__); gic_basic_init(numintrs, numvpes, intr_map, intr_map_size); gic_platform_init(numintrs, &gic_irq_controller); Loading