Loading drivers/clk/msm/clock-gcc-8996.c +0 −15 Original line number Diff line number Diff line Loading @@ -2216,19 +2216,6 @@ static struct branch_clk gcc_mmss_noc_cfg_ahb_clk = { }, }; static struct branch_clk gcc_mmss_sys_noc_axi_clk = { .cbcr_reg = GCC_MMSS_SYS_NOC_AXI_CBCR, .has_sibling = 1, .check_enable_bit = true, .base = &virt_base, .c = { .dbg_name = "gcc_mmss_sys_noc_axi_clk", .always_on = true, .ops = &clk_ops_branch, CLK_INIT(gcc_mmss_sys_noc_axi_clk.c), }, }; static struct branch_clk gcc_pcie_0_aux_clk = { .cbcr_reg = GCC_PCIE_0_AUX_CBCR, .has_sibling = 0, Loading Loading @@ -3183,7 +3170,6 @@ static struct mux_clk gcc_debug_mux = { { &gcc_ce1_ahb_m_clk.c, 0x009b }, { &measure_only_bimc_hmss_axi_clk.c, 0x00a5 }, { &gcc_periph_noc_usb20_ahb_clk.c, 0x0014 }, { &gcc_mmss_sys_noc_axi_clk.c, 0x0018 }, { &gcc_mmss_noc_cfg_ahb_clk.c, 0x0019 }, { &gcc_mmss_bimc_gfx_clk.c, 0x001c}, { &gcc_bimc_gfx_clk.c, 0x00af}, Loading Loading @@ -3510,7 +3496,6 @@ static struct clk_lookup msm_clocks_gcc_8996[] = { CLK_LIST(gcc_gp3_clk), CLK_LIST(gcc_hmss_rbcpr_clk), CLK_LIST(gcc_mmss_noc_cfg_ahb_clk), CLK_LIST(gcc_mmss_sys_noc_axi_clk), CLK_LIST(gcc_sys_noc_usb3_axi_clk), CLK_LIST(gcc_sys_noc_ufs_axi_clk), CLK_LIST(gcc_pcie_0_phy_reset), Loading include/dt-bindings/clock/msm-clocks-8996.h +0 −1 Original line number Diff line number Diff line Loading @@ -196,7 +196,6 @@ #define clk_gcc_gp2_clk 0x9bf83ffd #define clk_gcc_gp3_clk 0xec6539ee #define clk_gcc_hmss_rbcpr_clk 0x699183be #define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b #define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 #define clk_gcc_pcie_0_aux_clk 0x3d2e3ece #define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 Loading include/dt-bindings/clock/msm-clocks-hwio-8996.h +0 −1 Original line number Diff line number Diff line Loading @@ -463,7 +463,6 @@ #define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CTL (0x8101C) #define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR (0x7D010) #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR (0x7D014) #define GCC_MMSS_SYS_NOC_AXI_CBCR (0x09004) #define GCC_MMSS_NOC_CFG_AHB_CBCR (0x09008) #define GCC_USB3_CLKREF_EN (0x8800C) #define GCC_HDMI_CLKREF_EN (0x88000) Loading Loading
drivers/clk/msm/clock-gcc-8996.c +0 −15 Original line number Diff line number Diff line Loading @@ -2216,19 +2216,6 @@ static struct branch_clk gcc_mmss_noc_cfg_ahb_clk = { }, }; static struct branch_clk gcc_mmss_sys_noc_axi_clk = { .cbcr_reg = GCC_MMSS_SYS_NOC_AXI_CBCR, .has_sibling = 1, .check_enable_bit = true, .base = &virt_base, .c = { .dbg_name = "gcc_mmss_sys_noc_axi_clk", .always_on = true, .ops = &clk_ops_branch, CLK_INIT(gcc_mmss_sys_noc_axi_clk.c), }, }; static struct branch_clk gcc_pcie_0_aux_clk = { .cbcr_reg = GCC_PCIE_0_AUX_CBCR, .has_sibling = 0, Loading Loading @@ -3183,7 +3170,6 @@ static struct mux_clk gcc_debug_mux = { { &gcc_ce1_ahb_m_clk.c, 0x009b }, { &measure_only_bimc_hmss_axi_clk.c, 0x00a5 }, { &gcc_periph_noc_usb20_ahb_clk.c, 0x0014 }, { &gcc_mmss_sys_noc_axi_clk.c, 0x0018 }, { &gcc_mmss_noc_cfg_ahb_clk.c, 0x0019 }, { &gcc_mmss_bimc_gfx_clk.c, 0x001c}, { &gcc_bimc_gfx_clk.c, 0x00af}, Loading Loading @@ -3510,7 +3496,6 @@ static struct clk_lookup msm_clocks_gcc_8996[] = { CLK_LIST(gcc_gp3_clk), CLK_LIST(gcc_hmss_rbcpr_clk), CLK_LIST(gcc_mmss_noc_cfg_ahb_clk), CLK_LIST(gcc_mmss_sys_noc_axi_clk), CLK_LIST(gcc_sys_noc_usb3_axi_clk), CLK_LIST(gcc_sys_noc_ufs_axi_clk), CLK_LIST(gcc_pcie_0_phy_reset), Loading
include/dt-bindings/clock/msm-clocks-8996.h +0 −1 Original line number Diff line number Diff line Loading @@ -196,7 +196,6 @@ #define clk_gcc_gp2_clk 0x9bf83ffd #define clk_gcc_gp3_clk 0xec6539ee #define clk_gcc_hmss_rbcpr_clk 0x699183be #define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b #define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 #define clk_gcc_pcie_0_aux_clk 0x3d2e3ece #define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 Loading
include/dt-bindings/clock/msm-clocks-hwio-8996.h +0 −1 Original line number Diff line number Diff line Loading @@ -463,7 +463,6 @@ #define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CTL (0x8101C) #define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR (0x7D010) #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR (0x7D014) #define GCC_MMSS_SYS_NOC_AXI_CBCR (0x09004) #define GCC_MMSS_NOC_CFG_AHB_CBCR (0x09008) #define GCC_USB3_CLKREF_EN (0x8800C) #define GCC_HDMI_CLKREF_EN (0x88000) Loading