Loading drivers/gpu/drm/gma500/cdv_device.c +2 −0 Original line number Diff line number Diff line Loading @@ -494,6 +494,7 @@ static const struct psb_offset cdv_regmap[2] = { .conf = PIPEACONF, .src = PIPEASRC, .dpll = DPLL_A, .dpll_md = DPLL_A_MD, .htotal = HTOTAL_A, .hblank = HBLANK_A, .hsync = HSYNC_A, Loading @@ -518,6 +519,7 @@ static const struct psb_offset cdv_regmap[2] = { .conf = PIPEBCONF, .src = PIPEBSRC, .dpll = DPLL_B, .dpll_md = DPLL_B_MD, .htotal = HTOTAL_B, .hblank = HBLANK_B, .hsync = HSYNC_B, Loading drivers/gpu/drm/gma500/cdv_intel_display.c +135 −155 Original line number Diff line number Diff line Loading @@ -218,8 +218,7 @@ static int cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, struct cdv_intel_clock_t *clock, bool is_lvds) { struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc); int pipe = psb_crtc->pipe; u32 m, n_vco, p; int ret = 0; Loading Loading @@ -503,14 +502,12 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { struct drm_device *dev = crtc->dev; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); int pipe = psb_intel_crtc->pipe; const struct psb_offset *map = &dev_priv->regmap[pipe]; unsigned long start, offset; int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE); int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; u32 dspcntr; int ret = 0; Loading @@ -532,9 +529,9 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc, start = psbfb->gtt->offset; offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); REG_WRITE(dspstride, crtc->fb->pitches[0]); REG_WRITE(map->stride, crtc->fb->pitches[0]); dspcntr = REG_READ(dspcntr_reg); dspcntr = REG_READ(map->cntr); dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; switch (crtc->fb->bits_per_pixel) { Loading @@ -556,15 +553,15 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc, ret = -EINVAL; goto psb_intel_pipe_set_base_exit; } REG_WRITE(dspcntr_reg, dspcntr); REG_WRITE(map->cntr, dspcntr); dev_dbg(dev->dev, "Writing base %08lX %08lX %d %d\n", start, offset, x, y); REG_WRITE(dspbase, offset); REG_READ(dspbase); REG_WRITE(dspsurf, start); REG_READ(dspsurf); REG_WRITE(map->base, offset); REG_READ(map->base); REG_WRITE(map->surf, start); REG_READ(map->surf); psb_intel_pipe_cleaner: /* If there was a previous display we can now unpin it */ Loading Loading @@ -721,8 +718,7 @@ static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_psb_private *dev_priv = (struct drm_psb_private *)dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int palreg = PALETTE_A; int i; Loading Loading @@ -779,13 +775,10 @@ static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc) static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) { struct drm_device *dev = crtc->dev; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int pipe = psb_intel_crtc->pipe; int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE; int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; int pipestat_reg = (pipe == 0) ? PIPEASTAT : PIPEBSTAT; const struct psb_offset *map = &dev_priv->regmap[pipe]; u32 temp; /* XXX: When our outputs are all unaware of DPMS modes other than off Loading @@ -803,44 +796,44 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) psb_intel_crtc->active = true; /* Enable the DPLL */ temp = REG_READ(dpll_reg); temp = REG_READ(map->dpll); if ((temp & DPLL_VCO_ENABLE) == 0) { REG_WRITE(dpll_reg, temp); REG_READ(dpll_reg); REG_WRITE(map->dpll, temp); REG_READ(map->dpll); /* Wait for the clocks to stabilize. */ udelay(150); REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); REG_READ(map->dpll); /* Wait for the clocks to stabilize. */ udelay(150); REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); REG_READ(map->dpll); /* Wait for the clocks to stabilize. */ udelay(150); } /* Jim Bish - switch plan and pipe per scott */ /* Enable the plane */ temp = REG_READ(dspcntr_reg); temp = REG_READ(map->cntr); if ((temp & DISPLAY_PLANE_ENABLE) == 0) { REG_WRITE(dspcntr_reg, REG_WRITE(map->cntr, temp | DISPLAY_PLANE_ENABLE); /* Flush the plane changes */ REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); REG_WRITE(map->base, REG_READ(map->base)); } udelay(150); /* Enable the pipe */ temp = REG_READ(pipeconf_reg); temp = REG_READ(map->conf); if ((temp & PIPEACONF_ENABLE) == 0) REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); temp = REG_READ(pipestat_reg); temp = REG_READ(map->status); temp &= ~(0xFFFF); temp |= PIPE_FIFO_UNDERRUN; REG_WRITE(pipestat_reg, temp); REG_READ(pipestat_reg); REG_WRITE(map->status, temp); REG_READ(map->status); cdv_intel_update_watermark(dev, crtc); cdv_intel_crtc_load_lut(crtc); Loading Loading @@ -870,10 +863,10 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) cdv_intel_wait_for_vblank(dev); /* Next, disable display pipes */ temp = REG_READ(pipeconf_reg); temp = REG_READ(map->conf); if ((temp & PIPEACONF_ENABLE) != 0) { REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); REG_READ(pipeconf_reg); REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); REG_READ(map->conf); } /* Wait for vblank for the disable to take effect. */ Loading @@ -882,19 +875,19 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) udelay(150); /* Disable display plane */ temp = REG_READ(dspcntr_reg); temp = REG_READ(map->cntr); if ((temp & DISPLAY_PLANE_ENABLE) != 0) { REG_WRITE(dspcntr_reg, REG_WRITE(map->cntr, temp & ~DISPLAY_PLANE_ENABLE); /* Flush the plane changes */ REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); REG_READ(dspbase_reg); REG_WRITE(map->base, REG_READ(map->base)); REG_READ(map->base); } temp = REG_READ(dpll_reg); temp = REG_READ(map->dpll); if ((temp & DPLL_VCO_ENABLE) != 0) { REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); REG_READ(map->dpll); } /* Wait for the clocks to turn off. */ Loading Loading @@ -953,19 +946,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int pipe = psb_intel_crtc->pipe; int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; int dpll_md_reg = (psb_intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; const struct psb_offset *map = &dev_priv->regmap[pipe]; int refclk; struct cdv_intel_clock_t clock; u32 dpll = 0, dspcntr, pipeconf; Loading Loading @@ -1036,7 +1017,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, /* dpll |= (2 << 11); */ /* setup pipeconf */ pipeconf = REG_READ(pipeconf_reg); pipeconf = REG_READ(map->conf); /* Set up the display plane register */ dspcntr = DISPPLANE_GAMMA_ENABLE; Loading @@ -1049,8 +1030,8 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, dspcntr |= DISPLAY_PLANE_ENABLE; pipeconf |= PIPEACONF_ENABLE; REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); REG_READ(map->dpll); cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds); Loading Loading @@ -1094,48 +1075,48 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); drm_mode_debug_printmodeline(mode); REG_WRITE(dpll_reg, (REG_READ(dpll_reg) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); REG_READ(map->dpll); /* Wait for the clocks to stabilize. */ udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */ if (!(REG_READ(dpll_reg) & DPLL_LOCK)) { if (!(REG_READ(map->dpll) & DPLL_LOCK)) { dev_err(dev->dev, "Failed to get DPLL lock\n"); return -EBUSY; } { int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; REG_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); } REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16)); REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); /* pipesrc and dspsize control the size that is scaled from, * which should always be the user's requested size. */ REG_WRITE(dspsize_reg, REG_WRITE(map->size, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); REG_WRITE(dsppos_reg, 0); REG_WRITE(pipesrc_reg, REG_WRITE(map->pos, 0); REG_WRITE(map->src, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); REG_WRITE(pipeconf_reg, pipeconf); REG_READ(pipeconf_reg); REG_WRITE(map->conf, pipeconf); REG_READ(map->conf); cdv_intel_wait_for_vblank(dev); REG_WRITE(dspcntr_reg, dspcntr); REG_WRITE(map->cntr, dspcntr); /* Flush the plane changes */ { Loading @@ -1156,11 +1137,10 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, static void cdv_intel_crtc_save(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; /* struct drm_psb_private *dev_priv = (struct drm_psb_private *)dev->dev_private; */ struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; int pipeA = (psb_intel_crtc->pipe == 0); const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; uint32_t paletteReg; int i; Loading @@ -1169,25 +1149,25 @@ static void cdv_intel_crtc_save(struct drm_crtc *crtc) return; } crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR); crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF); crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC); crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0); crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1); crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B); crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B); crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B); crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B); crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B); crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B); crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B); crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE); crtc_state->saveDSPCNTR = REG_READ(map->cntr); crtc_state->savePIPECONF = REG_READ(map->conf); crtc_state->savePIPESRC = REG_READ(map->src); crtc_state->saveFP0 = REG_READ(map->fp0); crtc_state->saveFP1 = REG_READ(map->fp1); crtc_state->saveDPLL = REG_READ(map->dpll); crtc_state->saveHTOTAL = REG_READ(map->htotal); crtc_state->saveHBLANK = REG_READ(map->hblank); crtc_state->saveHSYNC = REG_READ(map->hsync); crtc_state->saveVTOTAL = REG_READ(map->vtotal); crtc_state->saveVBLANK = REG_READ(map->vblank); crtc_state->saveVSYNC = REG_READ(map->vsync); crtc_state->saveDSPSTRIDE = REG_READ(map->stride); /*NOTE: DSPSIZE DSPPOS only for psb*/ crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE); crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS); crtc_state->saveDSPSIZE = REG_READ(map->size); crtc_state->saveDSPPOS = REG_READ(map->pos); crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE); crtc_state->saveDSPBASE = REG_READ(map->base); DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", crtc_state->saveDSPCNTR, Loading @@ -1208,7 +1188,7 @@ static void cdv_intel_crtc_save(struct drm_crtc *crtc) crtc_state->saveDSPBASE ); paletteReg = pipeA ? PALETTE_A : PALETTE_B; paletteReg = map->palette; for (i = 0; i < 256; ++i) crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); } Loading @@ -1219,12 +1199,10 @@ static void cdv_intel_crtc_save(struct drm_crtc *crtc) static void cdv_intel_crtc_restore(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; /* struct drm_psb_private * dev_priv = (struct drm_psb_private *)dev->dev_private; */ struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */ int pipeA = (psb_intel_crtc->pipe == 0); const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; uint32_t paletteReg; int i; Loading @@ -1235,22 +1213,22 @@ static void cdv_intel_crtc_restore(struct drm_crtc *crtc) DRM_DEBUG( "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", REG_READ(pipeA ? DSPACNTR : DSPBCNTR), REG_READ(pipeA ? PIPEACONF : PIPEBCONF), REG_READ(pipeA ? PIPEASRC : PIPEBSRC), REG_READ(pipeA ? FPA0 : FPB0), REG_READ(pipeA ? FPA1 : FPB1), REG_READ(pipeA ? DPLL_A : DPLL_B), REG_READ(pipeA ? HTOTAL_A : HTOTAL_B), REG_READ(pipeA ? HBLANK_A : HBLANK_B), REG_READ(pipeA ? HSYNC_A : HSYNC_B), REG_READ(pipeA ? VTOTAL_A : VTOTAL_B), REG_READ(pipeA ? VBLANK_A : VBLANK_B), REG_READ(pipeA ? VSYNC_A : VSYNC_B), REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE), REG_READ(pipeA ? DSPASIZE : DSPBSIZE), REG_READ(pipeA ? DSPAPOS : DSPBPOS), REG_READ(pipeA ? DSPABASE : DSPBBASE) REG_READ(map->cntr), REG_READ(map->conf), REG_READ(map->src), REG_READ(map->fp0), REG_READ(map->fp1), REG_READ(map->dpll), REG_READ(map->htotal), REG_READ(map->hblank), REG_READ(map->hsync), REG_READ(map->vtotal), REG_READ(map->vblank), REG_READ(map->vsync), REG_READ(map->stride), REG_READ(map->size), REG_READ(map->pos), REG_READ(map->base) ); DRM_DEBUG( Loading @@ -1275,47 +1253,47 @@ static void cdv_intel_crtc_restore(struct drm_crtc *crtc) if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { REG_WRITE(pipeA ? DPLL_A : DPLL_B, REG_WRITE(map->dpll, crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); REG_READ(pipeA ? DPLL_A : DPLL_B); REG_READ(map->dpll); DRM_DEBUG("write dpll: %x\n", REG_READ(pipeA ? DPLL_A : DPLL_B)); REG_READ(map->dpll)); udelay(150); } REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0); REG_READ(pipeA ? FPA0 : FPB0); REG_WRITE(map->fp0, crtc_state->saveFP0); REG_READ(map->fp0); REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1); REG_READ(pipeA ? FPA1 : FPB1); REG_WRITE(map->fp1, crtc_state->saveFP1); REG_READ(map->fp1); REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL); REG_READ(pipeA ? DPLL_A : DPLL_B); REG_WRITE(map->dpll, crtc_state->saveDPLL); REG_READ(map->dpll); udelay(150); REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL); REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK); REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC); REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL); REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK); REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC); REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE); REG_WRITE(map->htotal, crtc_state->saveHTOTAL); REG_WRITE(map->hblank, crtc_state->saveHBLANK); REG_WRITE(map->hsync, crtc_state->saveHSYNC); REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); REG_WRITE(map->vblank, crtc_state->saveVBLANK); REG_WRITE(map->vsync, crtc_state->saveVSYNC); REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE); REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS); REG_WRITE(map->size, crtc_state->saveDSPSIZE); REG_WRITE(map->pos, crtc_state->saveDSPPOS); REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC); REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF); REG_WRITE(map->src, crtc_state->savePIPESRC); REG_WRITE(map->base, crtc_state->saveDSPBASE); REG_WRITE(map->conf, crtc_state->savePIPECONF); cdv_intel_wait_for_vblank(dev); REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR); REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); REG_WRITE(map->base, crtc_state->saveDSPBASE); cdv_intel_wait_for_vblank(dev); paletteReg = pipeA ? PALETTE_A : PALETTE_B; paletteReg = map->palette; for (i = 0; i < 256; ++i) REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); } Loading Loading @@ -1490,21 +1468,22 @@ static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock) static int cdv_intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) { struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int pipe = psb_intel_crtc->pipe; const struct psb_offset *map = &dev_priv->regmap[pipe]; u32 dpll; u32 fp; struct cdv_intel_clock_t clock; bool is_lvds; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; if (gma_power_begin(dev, false)) { dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); dpll = REG_READ(map->dpll); if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) fp = REG_READ((pipe == 0) ? FPA0 : FPB0); fp = REG_READ(map->fp0); else fp = REG_READ((pipe == 0) ? FPA1 : FPB1); fp = REG_READ(map->fp1); is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); gma_power_end(dev); } else { Loading Loading @@ -1570,19 +1549,20 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, { struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int pipe = psb_intel_crtc->pipe; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; const struct psb_offset *map = &dev_priv->regmap[pipe]; struct drm_display_mode *mode; int htot; int hsync; int vtot; int vsync; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; if (gma_power_begin(dev, false)) { htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B); vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); htot = REG_READ(map->htotal); hsync = REG_READ(map->hsync); vtot = REG_READ(map->vtotal); vsync = REG_READ(map->vsync); gma_power_end(dev); } else { htot = p->htotal; Loading Loading
drivers/gpu/drm/gma500/cdv_device.c +2 −0 Original line number Diff line number Diff line Loading @@ -494,6 +494,7 @@ static const struct psb_offset cdv_regmap[2] = { .conf = PIPEACONF, .src = PIPEASRC, .dpll = DPLL_A, .dpll_md = DPLL_A_MD, .htotal = HTOTAL_A, .hblank = HBLANK_A, .hsync = HSYNC_A, Loading @@ -518,6 +519,7 @@ static const struct psb_offset cdv_regmap[2] = { .conf = PIPEBCONF, .src = PIPEBSRC, .dpll = DPLL_B, .dpll_md = DPLL_B_MD, .htotal = HTOTAL_B, .hblank = HBLANK_B, .hsync = HSYNC_B, Loading
drivers/gpu/drm/gma500/cdv_intel_display.c +135 −155 Original line number Diff line number Diff line Loading @@ -218,8 +218,7 @@ static int cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, struct cdv_intel_clock_t *clock, bool is_lvds) { struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc); int pipe = psb_crtc->pipe; u32 m, n_vco, p; int ret = 0; Loading Loading @@ -503,14 +502,12 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { struct drm_device *dev = crtc->dev; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); int pipe = psb_intel_crtc->pipe; const struct psb_offset *map = &dev_priv->regmap[pipe]; unsigned long start, offset; int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE); int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; u32 dspcntr; int ret = 0; Loading @@ -532,9 +529,9 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc, start = psbfb->gtt->offset; offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); REG_WRITE(dspstride, crtc->fb->pitches[0]); REG_WRITE(map->stride, crtc->fb->pitches[0]); dspcntr = REG_READ(dspcntr_reg); dspcntr = REG_READ(map->cntr); dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; switch (crtc->fb->bits_per_pixel) { Loading @@ -556,15 +553,15 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc, ret = -EINVAL; goto psb_intel_pipe_set_base_exit; } REG_WRITE(dspcntr_reg, dspcntr); REG_WRITE(map->cntr, dspcntr); dev_dbg(dev->dev, "Writing base %08lX %08lX %d %d\n", start, offset, x, y); REG_WRITE(dspbase, offset); REG_READ(dspbase); REG_WRITE(dspsurf, start); REG_READ(dspsurf); REG_WRITE(map->base, offset); REG_READ(map->base); REG_WRITE(map->surf, start); REG_READ(map->surf); psb_intel_pipe_cleaner: /* If there was a previous display we can now unpin it */ Loading Loading @@ -721,8 +718,7 @@ static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_psb_private *dev_priv = (struct drm_psb_private *)dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int palreg = PALETTE_A; int i; Loading Loading @@ -779,13 +775,10 @@ static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc) static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) { struct drm_device *dev = crtc->dev; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int pipe = psb_intel_crtc->pipe; int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE; int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; int pipestat_reg = (pipe == 0) ? PIPEASTAT : PIPEBSTAT; const struct psb_offset *map = &dev_priv->regmap[pipe]; u32 temp; /* XXX: When our outputs are all unaware of DPMS modes other than off Loading @@ -803,44 +796,44 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) psb_intel_crtc->active = true; /* Enable the DPLL */ temp = REG_READ(dpll_reg); temp = REG_READ(map->dpll); if ((temp & DPLL_VCO_ENABLE) == 0) { REG_WRITE(dpll_reg, temp); REG_READ(dpll_reg); REG_WRITE(map->dpll, temp); REG_READ(map->dpll); /* Wait for the clocks to stabilize. */ udelay(150); REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); REG_READ(map->dpll); /* Wait for the clocks to stabilize. */ udelay(150); REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); REG_READ(map->dpll); /* Wait for the clocks to stabilize. */ udelay(150); } /* Jim Bish - switch plan and pipe per scott */ /* Enable the plane */ temp = REG_READ(dspcntr_reg); temp = REG_READ(map->cntr); if ((temp & DISPLAY_PLANE_ENABLE) == 0) { REG_WRITE(dspcntr_reg, REG_WRITE(map->cntr, temp | DISPLAY_PLANE_ENABLE); /* Flush the plane changes */ REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); REG_WRITE(map->base, REG_READ(map->base)); } udelay(150); /* Enable the pipe */ temp = REG_READ(pipeconf_reg); temp = REG_READ(map->conf); if ((temp & PIPEACONF_ENABLE) == 0) REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); temp = REG_READ(pipestat_reg); temp = REG_READ(map->status); temp &= ~(0xFFFF); temp |= PIPE_FIFO_UNDERRUN; REG_WRITE(pipestat_reg, temp); REG_READ(pipestat_reg); REG_WRITE(map->status, temp); REG_READ(map->status); cdv_intel_update_watermark(dev, crtc); cdv_intel_crtc_load_lut(crtc); Loading Loading @@ -870,10 +863,10 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) cdv_intel_wait_for_vblank(dev); /* Next, disable display pipes */ temp = REG_READ(pipeconf_reg); temp = REG_READ(map->conf); if ((temp & PIPEACONF_ENABLE) != 0) { REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); REG_READ(pipeconf_reg); REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); REG_READ(map->conf); } /* Wait for vblank for the disable to take effect. */ Loading @@ -882,19 +875,19 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) udelay(150); /* Disable display plane */ temp = REG_READ(dspcntr_reg); temp = REG_READ(map->cntr); if ((temp & DISPLAY_PLANE_ENABLE) != 0) { REG_WRITE(dspcntr_reg, REG_WRITE(map->cntr, temp & ~DISPLAY_PLANE_ENABLE); /* Flush the plane changes */ REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); REG_READ(dspbase_reg); REG_WRITE(map->base, REG_READ(map->base)); REG_READ(map->base); } temp = REG_READ(dpll_reg); temp = REG_READ(map->dpll); if ((temp & DPLL_VCO_ENABLE) != 0) { REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); REG_READ(map->dpll); } /* Wait for the clocks to turn off. */ Loading Loading @@ -953,19 +946,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int pipe = psb_intel_crtc->pipe; int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; int dpll_md_reg = (psb_intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; const struct psb_offset *map = &dev_priv->regmap[pipe]; int refclk; struct cdv_intel_clock_t clock; u32 dpll = 0, dspcntr, pipeconf; Loading Loading @@ -1036,7 +1017,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, /* dpll |= (2 << 11); */ /* setup pipeconf */ pipeconf = REG_READ(pipeconf_reg); pipeconf = REG_READ(map->conf); /* Set up the display plane register */ dspcntr = DISPPLANE_GAMMA_ENABLE; Loading @@ -1049,8 +1030,8 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, dspcntr |= DISPLAY_PLANE_ENABLE; pipeconf |= PIPEACONF_ENABLE; REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); REG_READ(map->dpll); cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds); Loading Loading @@ -1094,48 +1075,48 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); drm_mode_debug_printmodeline(mode); REG_WRITE(dpll_reg, (REG_READ(dpll_reg) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); REG_READ(dpll_reg); REG_WRITE(map->dpll, (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); REG_READ(map->dpll); /* Wait for the clocks to stabilize. */ udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */ if (!(REG_READ(dpll_reg) & DPLL_LOCK)) { if (!(REG_READ(map->dpll) & DPLL_LOCK)) { dev_err(dev->dev, "Failed to get DPLL lock\n"); return -EBUSY; } { int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; REG_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); } REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16)); REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); /* pipesrc and dspsize control the size that is scaled from, * which should always be the user's requested size. */ REG_WRITE(dspsize_reg, REG_WRITE(map->size, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); REG_WRITE(dsppos_reg, 0); REG_WRITE(pipesrc_reg, REG_WRITE(map->pos, 0); REG_WRITE(map->src, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); REG_WRITE(pipeconf_reg, pipeconf); REG_READ(pipeconf_reg); REG_WRITE(map->conf, pipeconf); REG_READ(map->conf); cdv_intel_wait_for_vblank(dev); REG_WRITE(dspcntr_reg, dspcntr); REG_WRITE(map->cntr, dspcntr); /* Flush the plane changes */ { Loading @@ -1156,11 +1137,10 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, static void cdv_intel_crtc_save(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; /* struct drm_psb_private *dev_priv = (struct drm_psb_private *)dev->dev_private; */ struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; int pipeA = (psb_intel_crtc->pipe == 0); const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; uint32_t paletteReg; int i; Loading @@ -1169,25 +1149,25 @@ static void cdv_intel_crtc_save(struct drm_crtc *crtc) return; } crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR); crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF); crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC); crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0); crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1); crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B); crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B); crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B); crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B); crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B); crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B); crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B); crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE); crtc_state->saveDSPCNTR = REG_READ(map->cntr); crtc_state->savePIPECONF = REG_READ(map->conf); crtc_state->savePIPESRC = REG_READ(map->src); crtc_state->saveFP0 = REG_READ(map->fp0); crtc_state->saveFP1 = REG_READ(map->fp1); crtc_state->saveDPLL = REG_READ(map->dpll); crtc_state->saveHTOTAL = REG_READ(map->htotal); crtc_state->saveHBLANK = REG_READ(map->hblank); crtc_state->saveHSYNC = REG_READ(map->hsync); crtc_state->saveVTOTAL = REG_READ(map->vtotal); crtc_state->saveVBLANK = REG_READ(map->vblank); crtc_state->saveVSYNC = REG_READ(map->vsync); crtc_state->saveDSPSTRIDE = REG_READ(map->stride); /*NOTE: DSPSIZE DSPPOS only for psb*/ crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE); crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS); crtc_state->saveDSPSIZE = REG_READ(map->size); crtc_state->saveDSPPOS = REG_READ(map->pos); crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE); crtc_state->saveDSPBASE = REG_READ(map->base); DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", crtc_state->saveDSPCNTR, Loading @@ -1208,7 +1188,7 @@ static void cdv_intel_crtc_save(struct drm_crtc *crtc) crtc_state->saveDSPBASE ); paletteReg = pipeA ? PALETTE_A : PALETTE_B; paletteReg = map->palette; for (i = 0; i < 256; ++i) crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); } Loading @@ -1219,12 +1199,10 @@ static void cdv_intel_crtc_save(struct drm_crtc *crtc) static void cdv_intel_crtc_restore(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; /* struct drm_psb_private * dev_priv = (struct drm_psb_private *)dev->dev_private; */ struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */ int pipeA = (psb_intel_crtc->pipe == 0); const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; uint32_t paletteReg; int i; Loading @@ -1235,22 +1213,22 @@ static void cdv_intel_crtc_restore(struct drm_crtc *crtc) DRM_DEBUG( "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", REG_READ(pipeA ? DSPACNTR : DSPBCNTR), REG_READ(pipeA ? PIPEACONF : PIPEBCONF), REG_READ(pipeA ? PIPEASRC : PIPEBSRC), REG_READ(pipeA ? FPA0 : FPB0), REG_READ(pipeA ? FPA1 : FPB1), REG_READ(pipeA ? DPLL_A : DPLL_B), REG_READ(pipeA ? HTOTAL_A : HTOTAL_B), REG_READ(pipeA ? HBLANK_A : HBLANK_B), REG_READ(pipeA ? HSYNC_A : HSYNC_B), REG_READ(pipeA ? VTOTAL_A : VTOTAL_B), REG_READ(pipeA ? VBLANK_A : VBLANK_B), REG_READ(pipeA ? VSYNC_A : VSYNC_B), REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE), REG_READ(pipeA ? DSPASIZE : DSPBSIZE), REG_READ(pipeA ? DSPAPOS : DSPBPOS), REG_READ(pipeA ? DSPABASE : DSPBBASE) REG_READ(map->cntr), REG_READ(map->conf), REG_READ(map->src), REG_READ(map->fp0), REG_READ(map->fp1), REG_READ(map->dpll), REG_READ(map->htotal), REG_READ(map->hblank), REG_READ(map->hsync), REG_READ(map->vtotal), REG_READ(map->vblank), REG_READ(map->vsync), REG_READ(map->stride), REG_READ(map->size), REG_READ(map->pos), REG_READ(map->base) ); DRM_DEBUG( Loading @@ -1275,47 +1253,47 @@ static void cdv_intel_crtc_restore(struct drm_crtc *crtc) if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { REG_WRITE(pipeA ? DPLL_A : DPLL_B, REG_WRITE(map->dpll, crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); REG_READ(pipeA ? DPLL_A : DPLL_B); REG_READ(map->dpll); DRM_DEBUG("write dpll: %x\n", REG_READ(pipeA ? DPLL_A : DPLL_B)); REG_READ(map->dpll)); udelay(150); } REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0); REG_READ(pipeA ? FPA0 : FPB0); REG_WRITE(map->fp0, crtc_state->saveFP0); REG_READ(map->fp0); REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1); REG_READ(pipeA ? FPA1 : FPB1); REG_WRITE(map->fp1, crtc_state->saveFP1); REG_READ(map->fp1); REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL); REG_READ(pipeA ? DPLL_A : DPLL_B); REG_WRITE(map->dpll, crtc_state->saveDPLL); REG_READ(map->dpll); udelay(150); REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL); REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK); REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC); REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL); REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK); REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC); REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE); REG_WRITE(map->htotal, crtc_state->saveHTOTAL); REG_WRITE(map->hblank, crtc_state->saveHBLANK); REG_WRITE(map->hsync, crtc_state->saveHSYNC); REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); REG_WRITE(map->vblank, crtc_state->saveVBLANK); REG_WRITE(map->vsync, crtc_state->saveVSYNC); REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE); REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS); REG_WRITE(map->size, crtc_state->saveDSPSIZE); REG_WRITE(map->pos, crtc_state->saveDSPPOS); REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC); REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF); REG_WRITE(map->src, crtc_state->savePIPESRC); REG_WRITE(map->base, crtc_state->saveDSPBASE); REG_WRITE(map->conf, crtc_state->savePIPECONF); cdv_intel_wait_for_vblank(dev); REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR); REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); REG_WRITE(map->base, crtc_state->saveDSPBASE); cdv_intel_wait_for_vblank(dev); paletteReg = pipeA ? PALETTE_A : PALETTE_B; paletteReg = map->palette; for (i = 0; i < 256; ++i) REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); } Loading Loading @@ -1490,21 +1468,22 @@ static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock) static int cdv_intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) { struct drm_psb_private *dev_priv = dev->dev_private; struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int pipe = psb_intel_crtc->pipe; const struct psb_offset *map = &dev_priv->regmap[pipe]; u32 dpll; u32 fp; struct cdv_intel_clock_t clock; bool is_lvds; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; if (gma_power_begin(dev, false)) { dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); dpll = REG_READ(map->dpll); if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) fp = REG_READ((pipe == 0) ? FPA0 : FPB0); fp = REG_READ(map->fp0); else fp = REG_READ((pipe == 0) ? FPA1 : FPB1); fp = REG_READ(map->fp1); is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); gma_power_end(dev); } else { Loading Loading @@ -1570,19 +1549,20 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, { struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); int pipe = psb_intel_crtc->pipe; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; const struct psb_offset *map = &dev_priv->regmap[pipe]; struct drm_display_mode *mode; int htot; int hsync; int vtot; int vsync; struct drm_psb_private *dev_priv = dev->dev_private; struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; if (gma_power_begin(dev, false)) { htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B); vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); htot = REG_READ(map->htotal); hsync = REG_READ(map->hsync); vtot = REG_READ(map->vtotal); vsync = REG_READ(map->vsync); gma_power_end(dev); } else { htot = p->htotal; Loading
Alan Cox <alan@linux.intel.com> Signed-off-by: