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Commit 211b8ab3 authored by Nicholas Troast's avatar Nicholas Troast
Browse files

power: qpnp-fg: add dt prop for therm delay



qcom,fg-therm-delay controls the time to delay before biasing the
battery thermistor.

Add this device tree property to expose this setting.

CRs-Fixed: 920744
Change-Id: I44d6210d7d53a5948b88da5a164ef8f9cef428d6
Signed-off-by: default avatarNicholas Troast <ntroast@codeaurora.org>
parent c2e38a43
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+2 −0
Original line number Diff line number Diff line
@@ -170,6 +170,8 @@ Parent node optional properties:
					gauge driver to detect the damaged battery
					when the safety-timer expires by using the
					coulomb count.
- qcom,fg-therm-delay-us:		The time in microseconds to delay battery
					thermistor biasing.

qcom,fg-soc node required properties:
- reg : offset and length of the PMIC peripheral register map.
+26 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@
#define NO_OTP_PROF_RELOAD	BIT(6)
#define REDO_FIRST_ESTIMATE	BIT(3)
#define RESTART_GO		BIT(0)
#define THERM_DELAY_MASK	0xE0

/* SUBTYPE definitions */
#define FG_SOC			0x9
@@ -194,6 +195,7 @@ enum fg_mem_setting_index {
	FG_MEM_SOC_MAX,
	FG_MEM_SOC_MIN,
	FG_MEM_BATT_LOW,
	FG_MEM_THERM_DELAY,
	FG_MEM_SETTING_MAX,
};

@@ -240,6 +242,7 @@ static struct fg_mem_setting settings[FG_MEM_SETTING_MAX] = {
	SETTING(SOC_MAX,	 0x458,   1,      85),
	SETTING(SOC_MIN,	 0x458,   2,      15),
	SETTING(BATT_LOW,	 0x458,   0,      4200),
	SETTING(THERM_DELAY,	 0x4AC,   3,      0),
};

#define DATA(_idx, _address, _offset, _length,  _value)	\
@@ -1505,6 +1508,19 @@ static u8 batt_to_setpoint_8b(int vbatt_mv)
	return DIV_ROUND_CLOSEST(val, 5);
}

static u8 therm_delay_to_setpoint(u32 delay_us)
{
	u8 val;

	if (delay_us < 2560)
		val = 0;
	else if (delay_us > 163840)
		val = 7;
	else
		val = ilog2(delay_us / 10) - 7;
	return val << 5;
}

static int get_current_time(unsigned long *now_tm_sec)
{
	struct rtc_time tm;
@@ -5019,6 +5035,7 @@ static int fg_of_init(struct fg_chip *chip)
	OF_READ_SETTING(FG_MEM_SOC_MAX, "fg-soc-max", rc, 1);
	OF_READ_SETTING(FG_MEM_SOC_MIN, "fg-soc-min", rc, 1);
	OF_READ_SETTING(FG_MEM_BATT_LOW, "fg-vbatt-low-threshold", rc, 1);
	OF_READ_SETTING(FG_MEM_THERM_DELAY, "fg-therm-delay-us", rc, 1);
	OF_READ_PROPERTY(chip->learning_data.max_increment,
			"cl-max-increment-deciperc", rc, 5);
	OF_READ_PROPERTY(chip->learning_data.max_decrement,
@@ -5838,6 +5855,15 @@ static int fg_common_hw_init(struct fg_chip *chip)
		return rc;
	}

	rc = fg_mem_masked_write(chip, settings[FG_MEM_THERM_DELAY].address,
		THERM_DELAY_MASK,
		therm_delay_to_setpoint(settings[FG_MEM_THERM_DELAY].value),
		settings[FG_MEM_THERM_DELAY].offset);
	if (rc) {
		pr_err("failed to write therm_delay rc=%d\n", rc);
		return rc;
	}

	if (chip->use_thermal_coefficients) {
		fg_mem_write(chip, chip->thermal_coefficients,
			THERMAL_COEFF_ADDR, THERMAL_COEFF_N_BYTES,