Loading arch/arm/boot/dts/qcom/msm8937-mdss.dtsi +6 −7 Original line number Original line Diff line number Diff line Loading @@ -41,7 +41,9 @@ qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>; qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>; qcom,mdss-has-panic-ctrl; qcom,mdss-has-panic-ctrl; qcom,mdss-per-pipe-panic-luts = <0xffff>, qcom,mdss-per-pipe-panic-luts = <0x000f>, <0xffff>, <0xfffc>, <0xff00>; <0xff00>; qcom,mdss-mdp-reg-offset = <0x00001000>; qcom,mdss-mdp-reg-offset = <0x00001000>; Loading Loading @@ -85,6 +87,7 @@ qcom,mdss-has-non-scalar-rgb; qcom,mdss-has-non-scalar-rgb; qcom,mdss-has-rotator-downscale; qcom,mdss-has-rotator-downscale; qcom,mdss-idle-power-collapse-enabled; qcom,mdss-idle-power-collapse-enabled; qcom,mdss-rot-block-size = <64>; clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>, clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>, Loading @@ -95,10 +98,6 @@ "core_clk", "vsync_clk"; "core_clk", "vsync_clk"; qcom,mdp-settings = <0x01190 0x00000000>, qcom,mdp-settings = <0x01190 0x00000000>, <0x012ac 0x00000404>, <0x012b4 0x00000444>, <0x012bc 0x40444444>, <0x012c4 0x00000044>, <0x0506c 0x00000000>, <0x0506c 0x00000000>, <0x1506c 0x00000000>, <0x1506c 0x00000000>, <0x1706c 0x00000000>, <0x1706c 0x00000000>, Loading Loading @@ -157,10 +156,10 @@ }; }; smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { compatible = "qcom,smmu_arm_mdp_unsec"; compatible = "qcom,smmu_mdp_unsec"; }; }; smmu_mdp_sec: qcom,smmu_mdp_sec_cb { smmu_mdp_sec: qcom,smmu_mdp_sec_cb { compatible = "qcom,smmu_arm_mdp_sec"; compatible = "qcom,smmu_mdp_sec"; }; }; mdss_fb0: qcom,mdss_fb_primary { mdss_fb0: qcom,mdss_fb_primary { Loading drivers/video/msm/mdss/mdss.h +1 −7 Original line number Original line Diff line number Diff line Loading @@ -155,6 +155,7 @@ enum mdss_hw_quirk { MDSS_QUIRK_DOWNSCALE_HANG, MDSS_QUIRK_DOWNSCALE_HANG, MDSS_QUIRK_DSC_RIGHT_ONLY_PU, MDSS_QUIRK_DSC_RIGHT_ONLY_PU, MDSS_QUIRK_DSC_2SLICE_PU_THRPUT, MDSS_QUIRK_DSC_2SLICE_PU_THRPUT, MDSS_QUIRK_DMA_BI_DIR, MDSS_QUIRK_MAX, MDSS_QUIRK_MAX, }; }; Loading @@ -176,12 +177,6 @@ enum mdss_qos_settings { MDSS_QOS_MAX, MDSS_QOS_MAX, }; }; enum mdss_smmu_version { MDSS_SMMU_V1, MDSS_SMMU_V2, MDSS_SMMU_ARM }; struct reg_bus_client { struct reg_bus_client { char name[MAX_CLIENT_NAME_LEN]; char name[MAX_CLIENT_NAME_LEN]; short usecase_ndx; short usecase_ndx; Loading @@ -196,7 +191,6 @@ struct mdss_smmu_client { struct reg_bus_client *reg_bus_clt; struct reg_bus_client *reg_bus_clt; bool domain_attached; bool domain_attached; bool handoff_pending; bool handoff_pending; enum mdss_smmu_version smmu_type; }; }; struct mdss_data_type; struct mdss_data_type; Loading drivers/video/msm/mdss/mdss_io_util.c +3 −0 Original line number Original line Diff line number Diff line Loading @@ -142,6 +142,9 @@ int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg, struct dss_vreg *curr_vreg = NULL; struct dss_vreg *curr_vreg = NULL; enum dss_vreg_type type; enum dss_vreg_type type; if (!in_vreg || !num_vreg) return rc; if (config) { if (config) { for (i = 0; i < num_vreg; i++) { for (i = 0; i < num_vreg; i++) { curr_vreg = &in_vreg[i]; curr_vreg = &in_vreg[i]; Loading drivers/video/msm/mdss/mdss_mdp.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -1281,6 +1281,7 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) mdata->has_ubwc = true; mdata->has_ubwc = true; mdata->pixel_ram_size = 38 * 1024; mdata->pixel_ram_size = 38 * 1024; set_bit(MDSS_QOS_OTLIM, mdata->mdss_qos_map); set_bit(MDSS_QOS_OTLIM, mdata->mdss_qos_map); mdss_set_quirk(mdata, MDSS_QUIRK_DMA_BI_DIR); break; break; default: default: mdata->max_target_zorder = 4; /* excluding base layer */ mdata->max_target_zorder = 4; /* excluding base layer */ Loading drivers/video/msm/mdss/mdss_mdp_splash_logo.c +3 −2 Original line number Original line Diff line number Diff line Loading @@ -88,7 +88,7 @@ static int mdss_mdp_splash_alloc_memory(struct msm_fb_data_type *mfd, } } sinfo->size = buf_size; sinfo->size = buf_size; dma_buf_begin_cpu_access(sinfo->dma_buf, 0, size, DMA_FROM_DEVICE); dma_buf_begin_cpu_access(sinfo->dma_buf, 0, size, DMA_BIDIRECTIONAL); sinfo->splash_buffer = dma_buf_kmap(sinfo->dma_buf, 0); sinfo->splash_buffer = dma_buf_kmap(sinfo->dma_buf, 0); if (IS_ERR(sinfo->splash_buffer)) { if (IS_ERR(sinfo->splash_buffer)) { pr_err("ion kernel memory mapping failed\n"); pr_err("ion kernel memory mapping failed\n"); Loading Loading @@ -132,7 +132,8 @@ static void mdss_mdp_splash_free_memory(struct msm_fb_data_type *mfd) if (!mdata || !mdata->iclient || !sinfo->dma_buf) if (!mdata || !mdata->iclient || !sinfo->dma_buf) return; return; dma_buf_end_cpu_access(sinfo->dma_buf, 0, sinfo->size, DMA_FROM_DEVICE); dma_buf_end_cpu_access(sinfo->dma_buf, 0, sinfo->size, DMA_BIDIRECTIONAL); dma_buf_kunmap(sinfo->dma_buf, 0, sinfo->splash_buffer); dma_buf_kunmap(sinfo->dma_buf, 0, sinfo->splash_buffer); mdss_smmu_unmap_dma_buf(sinfo->table, MDSS_IOMMU_DOMAIN_UNSECURE, 0, mdss_smmu_unmap_dma_buf(sinfo->table, MDSS_IOMMU_DOMAIN_UNSECURE, 0, Loading Loading
arch/arm/boot/dts/qcom/msm8937-mdss.dtsi +6 −7 Original line number Original line Diff line number Diff line Loading @@ -41,7 +41,9 @@ qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>; qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>; qcom,mdss-has-panic-ctrl; qcom,mdss-has-panic-ctrl; qcom,mdss-per-pipe-panic-luts = <0xffff>, qcom,mdss-per-pipe-panic-luts = <0x000f>, <0xffff>, <0xfffc>, <0xff00>; <0xff00>; qcom,mdss-mdp-reg-offset = <0x00001000>; qcom,mdss-mdp-reg-offset = <0x00001000>; Loading Loading @@ -85,6 +87,7 @@ qcom,mdss-has-non-scalar-rgb; qcom,mdss-has-non-scalar-rgb; qcom,mdss-has-rotator-downscale; qcom,mdss-has-rotator-downscale; qcom,mdss-idle-power-collapse-enabled; qcom,mdss-idle-power-collapse-enabled; qcom,mdss-rot-block-size = <64>; clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>, clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>, Loading @@ -95,10 +98,6 @@ "core_clk", "vsync_clk"; "core_clk", "vsync_clk"; qcom,mdp-settings = <0x01190 0x00000000>, qcom,mdp-settings = <0x01190 0x00000000>, <0x012ac 0x00000404>, <0x012b4 0x00000444>, <0x012bc 0x40444444>, <0x012c4 0x00000044>, <0x0506c 0x00000000>, <0x0506c 0x00000000>, <0x1506c 0x00000000>, <0x1506c 0x00000000>, <0x1706c 0x00000000>, <0x1706c 0x00000000>, Loading Loading @@ -157,10 +156,10 @@ }; }; smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { compatible = "qcom,smmu_arm_mdp_unsec"; compatible = "qcom,smmu_mdp_unsec"; }; }; smmu_mdp_sec: qcom,smmu_mdp_sec_cb { smmu_mdp_sec: qcom,smmu_mdp_sec_cb { compatible = "qcom,smmu_arm_mdp_sec"; compatible = "qcom,smmu_mdp_sec"; }; }; mdss_fb0: qcom,mdss_fb_primary { mdss_fb0: qcom,mdss_fb_primary { Loading
drivers/video/msm/mdss/mdss.h +1 −7 Original line number Original line Diff line number Diff line Loading @@ -155,6 +155,7 @@ enum mdss_hw_quirk { MDSS_QUIRK_DOWNSCALE_HANG, MDSS_QUIRK_DOWNSCALE_HANG, MDSS_QUIRK_DSC_RIGHT_ONLY_PU, MDSS_QUIRK_DSC_RIGHT_ONLY_PU, MDSS_QUIRK_DSC_2SLICE_PU_THRPUT, MDSS_QUIRK_DSC_2SLICE_PU_THRPUT, MDSS_QUIRK_DMA_BI_DIR, MDSS_QUIRK_MAX, MDSS_QUIRK_MAX, }; }; Loading @@ -176,12 +177,6 @@ enum mdss_qos_settings { MDSS_QOS_MAX, MDSS_QOS_MAX, }; }; enum mdss_smmu_version { MDSS_SMMU_V1, MDSS_SMMU_V2, MDSS_SMMU_ARM }; struct reg_bus_client { struct reg_bus_client { char name[MAX_CLIENT_NAME_LEN]; char name[MAX_CLIENT_NAME_LEN]; short usecase_ndx; short usecase_ndx; Loading @@ -196,7 +191,6 @@ struct mdss_smmu_client { struct reg_bus_client *reg_bus_clt; struct reg_bus_client *reg_bus_clt; bool domain_attached; bool domain_attached; bool handoff_pending; bool handoff_pending; enum mdss_smmu_version smmu_type; }; }; struct mdss_data_type; struct mdss_data_type; Loading
drivers/video/msm/mdss/mdss_io_util.c +3 −0 Original line number Original line Diff line number Diff line Loading @@ -142,6 +142,9 @@ int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg, struct dss_vreg *curr_vreg = NULL; struct dss_vreg *curr_vreg = NULL; enum dss_vreg_type type; enum dss_vreg_type type; if (!in_vreg || !num_vreg) return rc; if (config) { if (config) { for (i = 0; i < num_vreg; i++) { for (i = 0; i < num_vreg; i++) { curr_vreg = &in_vreg[i]; curr_vreg = &in_vreg[i]; Loading
drivers/video/msm/mdss/mdss_mdp.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -1281,6 +1281,7 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) mdata->has_ubwc = true; mdata->has_ubwc = true; mdata->pixel_ram_size = 38 * 1024; mdata->pixel_ram_size = 38 * 1024; set_bit(MDSS_QOS_OTLIM, mdata->mdss_qos_map); set_bit(MDSS_QOS_OTLIM, mdata->mdss_qos_map); mdss_set_quirk(mdata, MDSS_QUIRK_DMA_BI_DIR); break; break; default: default: mdata->max_target_zorder = 4; /* excluding base layer */ mdata->max_target_zorder = 4; /* excluding base layer */ Loading
drivers/video/msm/mdss/mdss_mdp_splash_logo.c +3 −2 Original line number Original line Diff line number Diff line Loading @@ -88,7 +88,7 @@ static int mdss_mdp_splash_alloc_memory(struct msm_fb_data_type *mfd, } } sinfo->size = buf_size; sinfo->size = buf_size; dma_buf_begin_cpu_access(sinfo->dma_buf, 0, size, DMA_FROM_DEVICE); dma_buf_begin_cpu_access(sinfo->dma_buf, 0, size, DMA_BIDIRECTIONAL); sinfo->splash_buffer = dma_buf_kmap(sinfo->dma_buf, 0); sinfo->splash_buffer = dma_buf_kmap(sinfo->dma_buf, 0); if (IS_ERR(sinfo->splash_buffer)) { if (IS_ERR(sinfo->splash_buffer)) { pr_err("ion kernel memory mapping failed\n"); pr_err("ion kernel memory mapping failed\n"); Loading Loading @@ -132,7 +132,8 @@ static void mdss_mdp_splash_free_memory(struct msm_fb_data_type *mfd) if (!mdata || !mdata->iclient || !sinfo->dma_buf) if (!mdata || !mdata->iclient || !sinfo->dma_buf) return; return; dma_buf_end_cpu_access(sinfo->dma_buf, 0, sinfo->size, DMA_FROM_DEVICE); dma_buf_end_cpu_access(sinfo->dma_buf, 0, sinfo->size, DMA_BIDIRECTIONAL); dma_buf_kunmap(sinfo->dma_buf, 0, sinfo->splash_buffer); dma_buf_kunmap(sinfo->dma_buf, 0, sinfo->splash_buffer); mdss_smmu_unmap_dma_buf(sinfo->table, MDSS_IOMMU_DOMAIN_UNSECURE, 0, mdss_smmu_unmap_dma_buf(sinfo->table, MDSS_IOMMU_DOMAIN_UNSECURE, 0, Loading