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Commit 1f9a0bd4 authored by Huang Ying's avatar Huang Ying Committed by H. Peter Anvin
Browse files

x86, mce: Rename MSR_IA32_MCx_CTL2 value 



Rename CMCI_EN to MCI_CTL2_CMCI_EN and CMCI_THRESHOLD_MASK to
MCI_CTL2_CMCI_THRESHOLD_MASK to make naming consistent.

Signed-off-by: default avatarHuang Ying <ying.huang@intel.com>
LKML-Reference: <1275977348.3444.659.camel@yhuang-dev.sh.intel.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent e44a21b7

arch/x86/include/asm/mce.h

+4 −0
Original line number Diff line number Diff line
@@ -38,6 +38,10 @@ 
#define MCM_ADDR_MEM	 3	/* memory address */

#define MCM_ADDR_GENERIC 7	/* generic */



/* CTL2 register defines */

#define MCI_CTL2_CMCI_EN		(1ULL << 30)

#define MCI_CTL2_CMCI_THRESHOLD_MASK	0xffffULL



#define MCJ_CTX_MASK		3

#define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)

#define MCJ_CTX_RANDOM		0    /* inject context: random */

arch/x86/include/asm/msr-index.h

+0 −3
Original line number Diff line number Diff line
@@ -94,9 +94,6 @@ 
#define MSR_IA32_MC0_CTL2		0x00000280

#define MSR_IA32_MCx_CTL2(x)		(MSR_IA32_MC0_CTL2 + (x))



#define CMCI_EN			(1ULL << 30)

#define CMCI_THRESHOLD_MASK		0xffffULL



#define MSR_P6_PERFCTR0			0x000000c1

#define MSR_P6_PERFCTR1			0x000000c2

#define MSR_P6_EVNTSEL0			0x00000186

arch/x86/kernel/cpu/mcheck/mce_intel.c

+4 −4
Original line number Diff line number Diff line
@@ -95,19 +95,19 @@ static void cmci_discover(int banks, int boot) 
		rdmsrl(MSR_IA32_MCx_CTL2(i), val);



		/* Already owned by someone else? */

		if (val & CMCI_EN) {

		if (val & MCI_CTL2_CMCI_EN) {

			if (test_and_clear_bit(i, owned) && !boot)

				print_update("SHD", &hdr, i);

			__clear_bit(i, __get_cpu_var(mce_poll_banks));

			continue;

		}



		val |= CMCI_EN | CMCI_THRESHOLD;

		val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD;

		wrmsrl(MSR_IA32_MCx_CTL2(i), val);

		rdmsrl(MSR_IA32_MCx_CTL2(i), val);



		/* Did the enable bit stick? -- the bank supports CMCI */

		if (val & CMCI_EN) {

		if (val & MCI_CTL2_CMCI_EN) {

			if (!test_and_set_bit(i, owned) && !boot)

				print_update("CMCI", &hdr, i);

			__clear_bit(i, __get_cpu_var(mce_poll_banks));
@@ -155,7 +155,7 @@ void cmci_clear(void) 
			continue;

		/* Disable CMCI */

		rdmsrl(MSR_IA32_MCx_CTL2(i), val);

		val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);

		val &= ~(MCI_CTL2_CMCI_EN|MCI_CTL2_CMCI_THRESHOLD_MASK);

		wrmsrl(MSR_IA32_MCx_CTL2(i), val);

		__clear_bit(i, __get_cpu_var(mce_banks_owned));

	}