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Commit 1f3f0618 authored by Senthil Balasubramanian's avatar Senthil Balasubramanian Committed by John W. Linville
Browse files

ath9k_hw: update the chip tests for AR9003 



The AR9003 family requires a change on the loop and can also skip
testing the PHY timing registers. This chip test can now be used
by all Atheros hardware families, including legacy. We can
eventually move this out to the generic ath module.

Signed-off-by: default avatarSenthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent ad7b8060

drivers/net/wireless/ath/ath9k/hw.c

+10 −3
Original line number Diff line number Diff line
@@ -297,18 +297,25 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah) 
	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);

}



/* This should work for all families including legacy */

static bool ath9k_hw_chip_test(struct ath_hw *ah)

{

	struct ath_common *common = ath9k_hw_common(ah);

	u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };

	u32 regAddr[2] = { AR_STA_ID0 };

	u32 regHold[2];

	u32 patternData[4] = { 0x55555555,

			       0xaaaaaaaa,

			       0x66666666,

			       0x99999999 };

	int i, j;

	int i, j, loop_max;



	for (i = 0; i < 2; i++) {

	if (!AR_SREV_9300_20_OR_LATER(ah)) {

		loop_max = 2;

		regAddr[1] = AR_PHY_BASE + (8 << 2);

	} else

		loop_max = 1;



	for (i = 0; i < loop_max; i++) {

		u32 addr = regAddr[i];

		u32 wrData, rdData;