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Commit 1f28fb92 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/dpm/btc: filter clocks based on voltage/clk dep tables 

Filter out mclk and sclk levels higher than listed in the clk
voltage dependency tables.  Supporting these clocks will require
additional driver tweaking that isn't supported yet.

See bug:
https://bugs.freedesktop.org/show_bug.cgi?id=68235



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7102e232

drivers/gpu/drm/radeon/btc_dpm.c

+34 −0
Original line number Diff line number Diff line
@@ -2097,6 +2097,7 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, 
	bool disable_mclk_switching;

	u32 mclk, sclk;

	u16 vddc, vddci;

	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;



	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||

	    btc_dpm_vblank_too_short(rdev))
@@ -2138,6 +2139,39 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, 
			ps->low.vddci = max_limits->vddci;

	}



	/* limit clocks to max supported clocks based on voltage dependency tables */

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,

							&max_sclk_vddc);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,

							&max_mclk_vddci);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,

							&max_mclk_vddc);



	if (max_sclk_vddc) {

		if (ps->low.sclk > max_sclk_vddc)

			ps->low.sclk = max_sclk_vddc;

		if (ps->medium.sclk > max_sclk_vddc)

			ps->medium.sclk = max_sclk_vddc;

		if (ps->high.sclk > max_sclk_vddc)

			ps->high.sclk = max_sclk_vddc;

	}

	if (max_mclk_vddci) {

		if (ps->low.mclk > max_mclk_vddci)

			ps->low.mclk = max_mclk_vddci;

		if (ps->medium.mclk > max_mclk_vddci)

			ps->medium.mclk = max_mclk_vddci;

		if (ps->high.mclk > max_mclk_vddci)

			ps->high.mclk = max_mclk_vddci;

	}

	if (max_mclk_vddc) {

		if (ps->low.mclk > max_mclk_vddc)

			ps->low.mclk = max_mclk_vddc;

		if (ps->medium.mclk > max_mclk_vddc)

			ps->medium.mclk = max_mclk_vddc;

		if (ps->high.mclk > max_mclk_vddc)

			ps->high.mclk = max_mclk_vddc;

	}



	/* XXX validate the min clocks required for display */



	if (disable_mclk_switching) {