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Commit 1f1bd5fc authored by Jeff Garzik's avatar Jeff Garzik
Browse files

[netdrvr] Remove long-unused bits from Becker template drivers 



Symbols such as PCI_USES_IO, PCI_ADDR0, etc. originated from Donald
Becker's net driver template, but have been long unused.  Remove.

In a few drivers, this allows the further eliminate of the pci_flags (or
just plain flags) member in the template driver probe structure.

Most of this logic is simply open-coded in most drivers, since it never
changes.

Made a few other cleanups while I was in there, too:
* constify, __devinitdata several PCI ID tables
* replace table terminating entries such as "{0,}," and "{NULL},"
  with a more-clean "{ }".

Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent a2b524b2

drivers/net/3c59x.c

+39 −40
Original line number Diff line number Diff line
@@ -375,8 +375,7 @@ limit of 4K. 
   of the drivers, and will likely be provided by some future kernel.

*/

enum pci_flags_bit {

	PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,

	PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,

	PCI_USES_MASTER=4,

};



enum {	IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
@@ -446,95 +445,95 @@ static struct vortex_chip_info { 
	int io_size;

} vortex_info_tbl[] __devinitdata = {

	{"3c590 Vortex 10Mbps",

	 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },

	 PCI_USES_MASTER, IS_VORTEX, 32, },

	{"3c592 EISA 10Mbps Demon/Vortex",					/* AKPM: from Don's 3c59x_cb.c 0.49H */

	 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },

	 PCI_USES_MASTER, IS_VORTEX, 32, },

	{"3c597 EISA Fast Demon/Vortex",					/* AKPM: from Don's 3c59x_cb.c 0.49H */

	 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },

	 PCI_USES_MASTER, IS_VORTEX, 32, },

	{"3c595 Vortex 100baseTx",

	 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },

	 PCI_USES_MASTER, IS_VORTEX, 32, },

	{"3c595 Vortex 100baseT4",

	 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },

	 PCI_USES_MASTER, IS_VORTEX, 32, },



	{"3c595 Vortex 100base-MII",

	 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },

	 PCI_USES_MASTER, IS_VORTEX, 32, },

	{"3c900 Boomerang 10baseT",

	 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },

	 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },

	{"3c900 Boomerang 10Mbps Combo",

	 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },

	 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },

	{"3c900 Cyclone 10Mbps TPO",						/* AKPM: from Don's 0.99M */

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	{"3c900 Cyclone 10Mbps Combo",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },



	{"3c900 Cyclone 10Mbps TPC",						/* AKPM: from Don's 0.99M */

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	{"3c900B-FL Cyclone 10base-FL",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	{"3c905 Boomerang 100baseTx",

	 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },

	 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },

	{"3c905 Boomerang 100baseT4",

	 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },

	 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },

	{"3c905B Cyclone 100baseTx",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },



	{"3c905B Cyclone 10/100/BNC",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },

	{"3c905B-FX Cyclone 100baseFx",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	{"3c905C Tornado",

	PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },

	PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },

	{"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },

	{"3c980 Cyclone",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },



	{"3c980C Python-T",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },

	{"3cSOHO100-TX Hurricane",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },

	{"3c555 Laptop Hurricane",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },

	{"3c556 Laptop Tornado",

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|

	 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|

									HAS_HWCKSM, 128, },

	{"3c556B Laptop Hurricane",

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|

	 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|

	                                WNO_XCVR_PWR|HAS_HWCKSM, 128, },



	{"3c575 [Megahertz] 10/100 LAN 	CardBus",

	PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },

	PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },

	{"3c575 Boomerang CardBus",

	 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },

	 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },

	{"3CCFE575BT Cyclone CardBus",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|

	 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|

									INVERT_LED_PWR|HAS_HWCKSM, 128, },

	{"3CCFE575CT Tornado CardBus",

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

	 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

									MAX_COLLISION_RESET|HAS_HWCKSM, 128, },

	{"3CCFE656 Cyclone CardBus",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

	 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

									INVERT_LED_PWR|HAS_HWCKSM, 128, },



	{"3CCFEM656B Cyclone+Winmodem CardBus",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

	 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

									INVERT_LED_PWR|HAS_HWCKSM, 128, },

	{"3CXFEM656C Tornado+Winmodem CardBus",			/* From pcmcia-cs-3.1.5 */

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

	 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|

									MAX_COLLISION_RESET|HAS_HWCKSM, 128, },

	{"3c450 HomePNA Tornado",						/* AKPM: from Don's 0.99Q */

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },

	{"3c920 Tornado",

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },

	{"3c982 Hydra Dual Port A",

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },

	 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },



	{"3c982 Hydra Dual Port B",

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },

	 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },

	{"3c905B-T4",

	 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },

	 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },

	{"3c920B-EMB-WNM Tornado",

	 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },

	 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },



	{NULL,}, /* NULL terminated list. */

};

drivers/net/dl2k.h

+4 −8
Original line number Diff line number Diff line
@@ -683,11 +683,6 @@ struct netdev_private { 
};



/* The station address location in the EEPROM. */

#ifdef MEM_MAPPING

#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)

#else

#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO  | PCI_ADDR0)

#endif

/* The struct pci_device_id consist of:

        vendor, device          Vendor and device ID to match (or PCI_ANY_ID)

        subvendor, subdevice    Subsystem vendor and device ID to match (or PCI_ANY_ID)
@@ -695,9 +690,10 @@ struct netdev_private { 
        class_mask              of the class are honored during the comparison.

        driver_data             Data private to the driver.

*/

static struct pci_device_id rio_pci_tbl[] = {

	{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},

	{0,}



static const struct pci_device_id rio_pci_tbl[] = {

	{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },

	{ }

};

MODULE_DEVICE_TABLE (pci, rio_pci_tbl);

#define TX_TIMEOUT  (4*HZ)

drivers/net/eepro100.c

+0 −5
Original line number Diff line number Diff line
@@ -278,11 +278,6 @@ having to sign an Intel NDA when I'm helping Intel sell their own product! 


static int speedo_found1(struct pci_dev *pdev, void __iomem *ioaddr, int fnd_cnt, int acpi_idle_state);



enum pci_flags_bit {

	PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,

	PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,

};



/* Offsets to the various registers.

   All accesses need not be longword aligned. */

enum speedo_offsets {

drivers/net/epic100.c

+3 −17
Original line number Diff line number Diff line
@@ -191,23 +191,10 @@ IVc. Errata 
*/





enum pci_id_flags_bits {

        /* Set PCI command register bits before calling probe1(). */

        PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,

        /* Read and map the single following PCI BAR. */

        PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,

        PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,

};



enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };



#define EPIC_TOTAL_SIZE 0x100

#define USE_IO_OPS 1

#ifdef USE_IO_OPS

#define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_IO|PCI_ADDR0

#else

#define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_MEM|PCI_ADDR1

#endif



typedef enum {

	SMSC_83C170_0,
@@ -218,7 +205,6 @@ typedef enum { 


struct epic_chip_info {

	const char *name;

	enum pci_id_flags_bits pci_flags;

        int io_size;                            /* Needed for I/O region check or ioremap(). */

        int drv_flags;                          /* Driver use, intended as capability flags. */

};
@@ -227,11 +213,11 @@ struct epic_chip_info { 
/* indexed by chip_t */

static const struct epic_chip_info pci_id_tbl[] = {

	{ "SMSC EPIC/100 83c170",

	 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | NO_MII | MII_PWRDWN },

	  EPIC_TOTAL_SIZE, TYPE2_INTR | NO_MII | MII_PWRDWN },

	{ "SMSC EPIC/100 83c170",

	 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR },

	  EPIC_TOTAL_SIZE, TYPE2_INTR },

	{ "SMSC EPIC/C 83c175",

	 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | MII_PWRDWN },

	  EPIC_TOTAL_SIZE, TYPE2_INTR | MII_PWRDWN },

};

drivers/net/fealnx.c

+0 −10
Original line number Diff line number Diff line
@@ -126,16 +126,6 @@ MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)"); 


#define MIN_REGION_SIZE 136



enum pci_flags_bit {

	PCI_USES_IO = 1,

	PCI_USES_MEM = 2,

	PCI_USES_MASTER = 4,

	PCI_ADDR0 = 0x10 << 0,

	PCI_ADDR1 = 0x10 << 1,

	PCI_ADDR2 = 0x10 << 2,

	PCI_ADDR3 = 0x10 << 3,

};



/* A chip capabilities table, matching the entries in pci_tbl[] above. */

enum chip_capability_flags {

	HAS_MII_XCVR,