Loading Documentation/devicetree/bindings/gpu/adreno-iommu.txt +3 −0 Original line number Diff line number Diff line Loading @@ -38,6 +38,8 @@ Optional properties: When not set we use per process pagetables - qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target for secure buffer allocation - qcom,secure_align_mask: A mask for determining how secure buffers need to be aligned Example: Loading @@ -50,6 +52,7 @@ Example: <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>; clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk"; num_cb = <2>; qcom,secure_align_mask = <0xfff>; retention; qcom,global_pt; Loading arch/arm/boot/dts/qcom/msm8996-gpu.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -186,6 +186,7 @@ clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "gpu_ahb_clk", "gcc_mmss_bimc_gfx_clk", "gcc_bimc_gfx_clk"; num_cb = <2>; qcom,secure_align_mask = <0xfff>; retention; iommu_kgsl_cb2: iommu_kgsl_cb2 { Loading drivers/gpu/msm/adreno.c +4 −0 Original line number Diff line number Diff line Loading @@ -250,6 +250,10 @@ static int kgsl_iommu_pdev_probe(struct platform_device *pdev) if (result) goto err; if (of_property_read_u32(pdev->dev.of_node, "qcom,secure_align_mask", &data->secure_align_mask)) data->secure_align_mask = 0xfff; if (!data->iommu_ctx_count) { KGSL_CORE_ERR( "dt: KGSL IOMMU context bank count cannot be zero\n"); Loading drivers/gpu/msm/adreno_profile.c +1 −1 Original line number Diff line number Diff line Loading @@ -131,7 +131,7 @@ static inline int _create_ib_ref(struct adreno_device *adreno_dev, { unsigned int *start = cmd; *cmd++ = cp_mem_packet(adreno_dev, CP_INDIRECT_BUFFER_PFD, 2, 1); *cmd++ = cp_mem_packet(adreno_dev, CP_INDIRECT_BUFFER_PFE, 2, 1); cmd += cp_gpuaddr(adreno_dev, cmd, (memdesc->gpuaddr + off)); *cmd++ = cnt; Loading drivers/gpu/msm/kgsl.c +6 −4 Original line number Diff line number Diff line Loading @@ -2532,6 +2532,7 @@ long kgsl_ioctl_map_user_mem(struct kgsl_device_private *dev_priv, struct kgsl_map_user_mem *param = data; struct kgsl_mem_entry *entry = NULL; struct kgsl_process_private *private = dev_priv->process_priv; struct kgsl_mmu *mmu = &dev_priv->device->mmu; unsigned int memtype; /* Loading @@ -2541,7 +2542,7 @@ long kgsl_ioctl_map_user_mem(struct kgsl_device_private *dev_priv, if (param->flags & KGSL_MEMFLAGS_SECURE) { /* Log message and return if context protection isn't enabled */ if (!kgsl_mmu_is_secured(&dev_priv->device->mmu)) { if (!kgsl_mmu_is_secured(mmu)) { dev_WARN_ONCE(dev_priv->device->dev, 1, "Secure buffer not supported"); return -EOPNOTSUPP; Loading Loading @@ -2608,10 +2609,11 @@ long kgsl_ioctl_map_user_mem(struct kgsl_device_private *dev_priv, goto error; if ((param->flags & KGSL_MEMFLAGS_SECURE) && !IS_ALIGNED(entry->memdesc.size, SZ_1M)) { (entry->memdesc.size & mmu->secure_align_mask)) { KGSL_DRV_ERR(dev_priv->device, "Secure buffer size %lld must be 1MB aligned", entry->memdesc.size); "Secure buffer size %lld not aligned to %x alignment", entry->memdesc.size, mmu->secure_align_mask + 1); result = -EINVAL; goto error_attach; } Loading Loading
Documentation/devicetree/bindings/gpu/adreno-iommu.txt +3 −0 Original line number Diff line number Diff line Loading @@ -38,6 +38,8 @@ Optional properties: When not set we use per process pagetables - qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target for secure buffer allocation - qcom,secure_align_mask: A mask for determining how secure buffers need to be aligned Example: Loading @@ -50,6 +52,7 @@ Example: <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>; clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk"; num_cb = <2>; qcom,secure_align_mask = <0xfff>; retention; qcom,global_pt; Loading
arch/arm/boot/dts/qcom/msm8996-gpu.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -186,6 +186,7 @@ clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "gpu_ahb_clk", "gcc_mmss_bimc_gfx_clk", "gcc_bimc_gfx_clk"; num_cb = <2>; qcom,secure_align_mask = <0xfff>; retention; iommu_kgsl_cb2: iommu_kgsl_cb2 { Loading
drivers/gpu/msm/adreno.c +4 −0 Original line number Diff line number Diff line Loading @@ -250,6 +250,10 @@ static int kgsl_iommu_pdev_probe(struct platform_device *pdev) if (result) goto err; if (of_property_read_u32(pdev->dev.of_node, "qcom,secure_align_mask", &data->secure_align_mask)) data->secure_align_mask = 0xfff; if (!data->iommu_ctx_count) { KGSL_CORE_ERR( "dt: KGSL IOMMU context bank count cannot be zero\n"); Loading
drivers/gpu/msm/adreno_profile.c +1 −1 Original line number Diff line number Diff line Loading @@ -131,7 +131,7 @@ static inline int _create_ib_ref(struct adreno_device *adreno_dev, { unsigned int *start = cmd; *cmd++ = cp_mem_packet(adreno_dev, CP_INDIRECT_BUFFER_PFD, 2, 1); *cmd++ = cp_mem_packet(adreno_dev, CP_INDIRECT_BUFFER_PFE, 2, 1); cmd += cp_gpuaddr(adreno_dev, cmd, (memdesc->gpuaddr + off)); *cmd++ = cnt; Loading
drivers/gpu/msm/kgsl.c +6 −4 Original line number Diff line number Diff line Loading @@ -2532,6 +2532,7 @@ long kgsl_ioctl_map_user_mem(struct kgsl_device_private *dev_priv, struct kgsl_map_user_mem *param = data; struct kgsl_mem_entry *entry = NULL; struct kgsl_process_private *private = dev_priv->process_priv; struct kgsl_mmu *mmu = &dev_priv->device->mmu; unsigned int memtype; /* Loading @@ -2541,7 +2542,7 @@ long kgsl_ioctl_map_user_mem(struct kgsl_device_private *dev_priv, if (param->flags & KGSL_MEMFLAGS_SECURE) { /* Log message and return if context protection isn't enabled */ if (!kgsl_mmu_is_secured(&dev_priv->device->mmu)) { if (!kgsl_mmu_is_secured(mmu)) { dev_WARN_ONCE(dev_priv->device->dev, 1, "Secure buffer not supported"); return -EOPNOTSUPP; Loading Loading @@ -2608,10 +2609,11 @@ long kgsl_ioctl_map_user_mem(struct kgsl_device_private *dev_priv, goto error; if ((param->flags & KGSL_MEMFLAGS_SECURE) && !IS_ALIGNED(entry->memdesc.size, SZ_1M)) { (entry->memdesc.size & mmu->secure_align_mask)) { KGSL_DRV_ERR(dev_priv->device, "Secure buffer size %lld must be 1MB aligned", entry->memdesc.size); "Secure buffer size %lld not aligned to %x alignment", entry->memdesc.size, mmu->secure_align_mask + 1); result = -EINVAL; goto error_attach; } Loading