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Commit 1eb8dfec authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: fix Haswell DP M/N registers 



We have to write the correct values inside intel_dp_set_m_n and then
prevent these values from being overwritten later.

V2: Unconfuse double negation.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a836bdf9

drivers/gpu/drm/i915/intel_display.c

+2 −1
Original line number Diff line number Diff line
@@ -5356,6 +5356,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, 


	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);



	if (!is_dp || is_cpu_edp)

		ironlake_set_m_n(crtc, mode, adjusted_mode);



	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))

drivers/gpu/drm/i915/intel_dp.c

+6 −1
Original line number Diff line number Diff line
@@ -816,7 +816,12 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 
	intel_dp_compute_m_n(intel_crtc->bpp, lane_count,

			     mode->clock, adjusted_mode->clock, &m_n);



	if (HAS_PCH_SPLIT(dev)) {

	if (IS_HASWELL(dev)) {

		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);

		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);

		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);

	} else if (HAS_PCH_SPLIT(dev)) {

		I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);

		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);