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Commit 1ea649de authored by raghavendra ambadas's avatar raghavendra ambadas Committed by Gerrit - the friendly Code Review server
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msm: mdss: enable pll regulator during phy config 



Make sure to enable the pll digital block during phy on sequence.
This fixes some corruption observed as part of resume for cmd mode
dual dsi panel, where panel does not support phy power off during suspend.

Change-Id: I246917fc06e9fe79a952fe28296de3813a2e2081
Signed-off-by: default avatarRaghavendra Ambadas <rambad@codeaurora.org>
parent 37cba443

drivers/video/msm/mdss/msm_mdss_io_8974.c

+9 −1
Original line number Diff line number Diff line
@@ -1035,6 +1035,8 @@ static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl) 
	int j, off, ln, cnt, ln_off;

	char *ip;

	void __iomem *base;

	u32 data;

	struct mdss_panel_info *pinfo;



	pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db);
@@ -1118,7 +1120,13 @@ static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl) 
			mdss_dsi_8996_pll_source_standalone(ctrl);

	}



	pinfo = &ctrl->panel_data.panel_info;

	if (!(pinfo->allow_phy_power_off) && (pinfo->type == MIPI_CMD_PANEL)) {

		data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0);

		MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data | 0x7f);

	} else {

		MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f);

	}

	wmb(); /* make sure registers committed */

}