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Commit 1e662353 authored by Linus Walleij's avatar Linus Walleij
Browse files

ARM: ux500: move MMC/SD/SDIO pin control to the device tree 



This moves the static, device-tied pin control configuration
out of the board file board-mop500-pins.c and into the device
tree. Add entries for SDI1 and SDI2 on the Snowball so that the
WLAN pins on SDI1 can be used further on, and the unused pins
on SDI2 can be put to sleep.

Cc: Lee Jones <lee.jones@linaro.org>
Cc: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 96fee13f

arch/arm/boot/dts/ste-href-family-pinctrl.dtsi

+211 −0
Original line number Diff line number Diff line
@@ -214,6 +214,217 @@ 
					};

				};

			};



			/* Settings for all MMC/SD/SDIO default and sleep states */

			sdi0 {

				/* This is the external SD card slot, 4 bits wide */

				sdi0_default_mode: sdi0_default {

					default_mux {

						ste,function = "mc0";

						ste,pins = "mc0_a_1";

					};

					default_cfg1 {

						ste,pins =

						"GPIO18_AC2", /* CMDDIR */

						"GPIO19_AC1", /* DAT0DIR */

						"GPIO20_AB4"; /* DAT2DIR */

						ste,config = <&out_hi>;

					};

					default_cfg2 {

						ste,pins = "GPIO22_AA3"; /* FBCLK */

						ste,config = <&in_nopull>;

					};

					default_cfg3 {

						ste,pins = "GPIO23_AA4"; /* CLK */

						ste,config = <&out_lo>;

					};

					default_cfg4 {

						ste,pins =

						"GPIO24_AB2", /* CMD */

						"GPIO25_Y4", /* DAT0 */

						"GPIO26_Y2", /* DAT1 */

						"GPIO27_AA2", /* DAT2 */

						"GPIO28_AA1"; /* DAT3 */

						ste,config = <&in_pu>;

					};

				};



				sdi0_sleep_mode: sdi0_sleep {

					sleep_cfg1 {

						ste,pins =

						"GPIO18_AC2", /* CMDDIR */

						"GPIO19_AC1", /* DAT0DIR */

						"GPIO20_AB4"; /* DAT2DIR */

						ste,config = <&slpm_out_hi_wkup_pdis>;

					};

					sleep_cfg2 {

						ste,pins =

						"GPIO22_AA3", /* FBCLK */

						"GPIO24_AB2", /* CMD */

						"GPIO25_Y4", /* DAT0 */

						"GPIO26_Y2", /* DAT1 */

						"GPIO27_AA2", /* DAT2 */

						"GPIO28_AA1"; /* DAT3 */

						ste,config = <&slpm_in_wkup_pdis>;

					};

					sleep_cfg3 {

						ste,pins = "GPIO23_AA4"; /* CLK */

						ste,config = <&slpm_out_lo_wkup_pdis>;

					};

				};

			};



			sdi1 {

				/* This is the WLAN SDIO 4 bits wide */

				sdi1_default_mode: sdi1_default {

					default_mux {

						ste,function = "mc1";

						ste,pins = "mc1_a_1";

					};

					default_cfg1 {

						ste,pins = "GPIO208_AH16"; /* CLK */

						ste,config = <&out_lo>;

					};

					default_cfg2 {

						ste,pins = "GPIO209_AG15"; /* FBCLK */

						ste,config = <&in_nopull>;

					};

					default_cfg3 {

						ste,pins =

						"GPIO210_AJ15", /* CMD */

						"GPIO211_AG14", /* DAT0 */

						"GPIO212_AF13", /* DAT1 */

						"GPIO213_AG13", /* DAT2 */

						"GPIO214_AH15"; /* DAT3 */

						ste,config = <&in_pu>;

					};

				};



				sdi1_sleep_mode: sdi1_sleep {

					sleep_cfg1 {

						ste,pins = "GPIO208_AH16"; /* CLK */

						ste,config = <&slpm_out_lo_wkup_pdis>;

					};

					sleep_cfg2 {

						ste,pins =

						"GPIO209_AG15", /* FBCLK */

						"GPIO210_AJ15", /* CMD */

						"GPIO211_AG14", /* DAT0 */

						"GPIO212_AF13", /* DAT1 */

						"GPIO213_AG13", /* DAT2 */

						"GPIO214_AH15"; /* DAT3 */

						ste,config = <&slpm_in_wkup_pdis>;

					};

				};

			};



			sdi2 {

				/* This is the eMMC 8 bits wide, usually PoP eMMC */

				sdi2_default_mode: sdi2_default {

					default_mux {

						ste,function = "mc2";

						ste,pins = "mc2_a_1";

					};

					default_cfg1 {

						ste,pins = "GPIO128_A5"; /* CLK */

						ste,config = <&out_lo>;

					};

					default_cfg2 {

						ste,pins = "GPIO130_C8"; /* FBCLK */

						ste,config = <&in_nopull>;

					};

					default_cfg3 {

						ste,pins =

						"GPIO129_B4", /* CMD */

						"GPIO131_A12", /* DAT0 */

						"GPIO132_C10", /* DAT1 */

						"GPIO133_B10", /* DAT2 */

						"GPIO134_B9", /* DAT3 */

						"GPIO135_A9", /* DAT4 */

						"GPIO136_C7", /* DAT5 */

						"GPIO137_A7", /* DAT6 */

						"GPIO138_C5"; /* DAT7 */

						ste,config = <&in_pu>;

					};

				};



				sdi2_sleep_mode: sdi2_sleep {

					sleep_cfg1 {

						ste,pins = "GPIO128_A5"; /* CLK */

						ste,config = <&out_lo_wkup_pdis>;

					};

					sleep_cfg2 {

						ste,pins =

						"GPIO130_C8", /* FBCLK */

						"GPIO129_B4"; /* CMD */

						ste,config = <&in_wkup_pdis_en>;

					};

					sleep_cfg3 {

						ste,pins =

						"GPIO131_A12", /* DAT0 */

						"GPIO132_C10", /* DAT1 */

						"GPIO133_B10", /* DAT2 */

						"GPIO134_B9", /* DAT3 */

						"GPIO135_A9", /* DAT4 */

						"GPIO136_C7", /* DAT5 */

						"GPIO137_A7", /* DAT6 */

						"GPIO138_C5"; /* DAT7 */

						ste,config = <&in_wkup_pdis>;

					};

				};

			};



			sdi4 {

				/* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */

				sdi4_default_mode: sdi4_default {

					default_mux {

						ste,function = "mc4";

						ste,pins = "mc4_a_1";

					};

					default_cfg1 {

						ste,pins = "GPIO203_AE23"; /* CLK */

						ste,config = <&out_lo>;

					};

					default_cfg2 {

						ste,pins = "GPIO202_AF25"; /* FBCLK */

						ste,config = <&in_nopull>;

					};

					default_cfg3 {

						ste,pins =

						"GPIO201_AF24", /* CMD */

						"GPIO200_AH26", /* DAT0 */

						"GPIO199_AH23", /* DAT1 */

						"GPIO198_AG25", /* DAT2 */

						"GPIO197_AH24", /* DAT3 */

						"GPIO207_AJ23", /* DAT4 */

						"GPIO206_AG24", /* DAT5 */

						"GPIO205_AG23", /* DAT6 */

						"GPIO204_AF23"; /* DAT7 */

						ste,config = <&in_pu>;

					};

				};



				sdi4_sleep_mode: sdi4_sleep {

					sleep_cfg1 {

						ste,pins = "GPIO203_AE23"; /* CLK */

						ste,config = <&out_lo_wkup_pdis>;

					};

					sleep_cfg2 {

						ste,pins =

						"GPIO202_AF25", /* FBCLK */

						"GPIO201_AF24", /* CMD */

						"GPIO200_AH26", /* DAT0 */

						"GPIO199_AH23", /* DAT1 */

						"GPIO198_AG25", /* DAT2 */

						"GPIO197_AH24", /* DAT3 */

						"GPIO207_AJ23", /* DAT4 */

						"GPIO206_AG24", /* DAT5 */

						"GPIO205_AG23", /* DAT6 */

						"GPIO204_AF23"; /* DAT7 */

						ste,config = <&slpm_in_wkup_pdis>;

					};

				};

			};

		};

	};

};

arch/arm/boot/dts/ste-href.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -125,6 +125,9 @@ 
			mmc-cap-mmc-highspeed;

			vmmc-supply = <&ab8500_ldo_aux3_reg>;

			vqmmc-supply = <&vmmci>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&sdi0_default_mode>;

			pinctrl-1 = <&sdi0_sleep_mode>;



			cd-gpios  = <&tc3589x_gpio 3 0x4>;
@@ -136,6 +139,9 @@ 
			arm,primecell-periphid = <0x10480180>;

			max-frequency = <100000000>;

			bus-width = <4>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&sdi1_default_mode>;

			pinctrl-1 = <&sdi1_sleep_mode>;



			status = "okay";

		};
@@ -146,6 +152,9 @@ 
			max-frequency = <100000000>;

			bus-width = <8>;

			mmc-cap-mmc-highspeed;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&sdi2_default_mode>;

			pinctrl-1 = <&sdi2_sleep_mode>;



			status = "okay";

		};
@@ -157,6 +166,9 @@ 
			bus-width = <8>;

			mmc-cap-mmc-highspeed;

			vmmc-supply = <&ab8500_ldo_aux2_reg>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&sdi4_default_mode>;

			pinctrl-1 = <&sdi4_sleep_mode>;



			status = "okay";

		};

arch/arm/boot/dts/ste-hrefprev60.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -55,5 +55,22 @@ 


			status = "okay";

		};



		pinctrl {

			sdi0 {

				/* This additional pin needed on early MOP500 and HREFs previous to v60 */

				sdi0_default_mode: sdi0_default {

					hrefprev60_mux {

						ste,function = "mc0";

						ste,pins = "mc0dat31dir_a_1";

					};

					hrefprev60_cfg1 {

						ste,pins = "GPIO21_AB3"; /* DAT31DIR */

						ste,config = <&out_hi>;

					};



				};

			};

		};

	};

};

arch/arm/boot/dts/ste-hrefv60plus.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -66,5 +66,17 @@ 


			status = "okay";

		};



		pinctrl {

			sdi0 {

				/* SD card detect GPIO pin, extend default state */

				sdi0_default_mode: sdi0_default {

					default_hrefv60_cfg1 {

						ste,pins = "GPIO95_E8";

						ste,config = <&gpio_in_pu>;

					};

				};

			};

		};

	};

};

arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -68,6 +68,13 @@ 
		ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;

	};



	slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis {

		ste,sleep = <SLPM_ENABLED>;

		ste,sleep-output = <SLPM_OUTPUT_LOW>;

		ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;

		ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;

	};



	slpm_out_wkup_pdis: slpm_out_wkup_pdis {

		ste,sleep = <SLPM_ENABLED>;

		ste,sleep-output = <SLPM_DIR_OUTPUT>;
@@ -81,6 +88,18 @@ 
		ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;

	};



	in_wkup_pdis_en: in_wkup_pdis_en {

		ste,sleep-input = <SLPM_DIR_INPUT>;

		ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;

		ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;

	};



	out_lo_wkup_pdis: out_lo_wkup_pdis {

		ste,sleep-output = <SLPM_OUTPUT_LOW>;

		ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;

		ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;

	};



	out_hi_wkup_pdis: out_hi_wkup_pdis {

		ste,sleep-output = <SLPM_OUTPUT_HIGH>;

		ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;