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Commit 1e33dc64 authored by Winkler, Tomas's avatar Winkler, Tomas Committed by John W. Linville
Browse files

iwl3945: use hw_params.rx_buf_size



This patch makes 3945 use of hw_params.rx_buf_size instead of
IWL_RX_BUF_SIZE. It also renames IWL_RX_BUF_SIZE to IWL_RX_BUF_SIZE_3K
and moves rx buffer defines into iwl-fh.h.

Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarZhu Yi <yi.zhu@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent d45aadd0
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+1 −1
Original line number Diff line number Diff line
@@ -2485,7 +2485,7 @@ int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
		return -ENOMEM;
	}

	priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE;
	priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
	priv->hw_params.max_pkt_size = 2342;
	priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
	priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
+0 −1
Original line number Diff line number Diff line
@@ -96,7 +96,6 @@ enum iwl3945_antenna {
 * else RTS for data/management frames where MPDU is larger
 *   than RTS value.
 */
#define IWL_RX_BUF_SIZE           3000U
#define DEFAULT_RTS_THRESHOLD     2347U
#define MIN_RTS_THRESHOLD         0U
#define MAX_RTS_THRESHOLD         2347U
+0 −13
Original line number Diff line number Diff line
@@ -110,19 +110,6 @@

#define IWL_DEFAULT_TX_RETRY  15

#define RX_QUEUE_SIZE                         256
#define RX_QUEUE_MASK                         255
#define RX_QUEUE_SIZE_LOG                     8

/*
 * RX related structures and functions
 */
#define RX_FREE_BUFFERS 64
#define RX_LOW_WATERMARK 8

/* Size of one Rx buffer in host DRAM */
#define IWL_RX_BUF_SIZE_4K (4 * 1024)
#define IWL_RX_BUF_SIZE_8K (8 * 1024)

/* Sizes and addresses for instruction and data memory (SRAM) in
 * 4965's embedded processor.  Driver access is via HBUS_TARG_MEM_* regs. */
+15 −0
Original line number Diff line number Diff line
@@ -399,6 +399,21 @@
 */
#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN	(0x00000002)

#define RX_QUEUE_SIZE                         256
#define RX_QUEUE_MASK                         255
#define RX_QUEUE_SIZE_LOG                     8

/*
 * RX related structures and functions
 */
#define RX_FREE_BUFFERS 64
#define RX_LOW_WATERMARK 8

/* Size of one Rx buffer in host DRAM */
#define IWL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
#define IWL_RX_BUF_SIZE_4K (4 * 1024)
#define IWL_RX_BUF_SIZE_8K (8 * 1024)

/**
 * struct iwl_rb_status - reseve buffer status
 * 	host memory mapped FH registers
+9 −6
Original line number Diff line number Diff line
@@ -3281,7 +3281,8 @@ static void iwl3945_rx_allocate(struct iwl_priv *priv)

		/* Alloc a new receive buffer */
		rxb->skb =
		    alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
		    alloc_skb(priv->hw_params.rx_buf_size,
				__GFP_NOWARN | GFP_ATOMIC);
		if (!rxb->skb) {
			if (net_ratelimit())
				IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
@@ -3303,9 +3304,10 @@ static void iwl3945_rx_allocate(struct iwl_priv *priv)
		list_del(element);

		/* Get physical address of RB/SKB */
		rxb->real_dma_addr =
		    pci_map_single(priv->pci_dev, rxb->skb->data,
				   IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
		rxb->real_dma_addr = pci_map_single(priv->pci_dev,
						rxb->skb->data,
						priv->hw_params.rx_buf_size,
						PCI_DMA_FROMDEVICE);
		list_add_tail(&rxb->list, &rxq->rx_free);
		rxq->free_count++;
	}
@@ -3454,7 +3456,7 @@ static void iwl3945_rx_handle(struct iwl_priv *priv)
		rxq->queue[i] = NULL;

		pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
					    IWL_RX_BUF_SIZE,
					    priv->hw_params.rx_buf_size,
					    PCI_DMA_FROMDEVICE);
		pkt = (struct iwl_rx_packet *)rxb->skb->data;

@@ -3504,7 +3506,8 @@ static void iwl3945_rx_handle(struct iwl_priv *priv)
		}

		pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
				 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
				priv->hw_params.rx_buf_size,
				PCI_DMA_FROMDEVICE);
		spin_lock_irqsave(&rxq->lock, flags);
		list_add_tail(&rxb->list, &priv->rxq.rx_used);
		spin_unlock_irqrestore(&rxq->lock, flags);