Merge branch 'l2x0' of rmk tree into prima2-l2x0

* ARM L2 Cache Controller

ARM cores often have a separate level 2 cache controller. There are various

implementations of the L2 cache controller with compatible programming models.

The ARM L2 cache representation in the device tree should be done as follows:

Required properties:

- compatible : should be one of:

	"arm,pl310-cache"

	"arm,l220-cache"

	"arm,l210-cache"

- cache-unified : Specifies the cache is a unified cache.

- cache-level : Should be set to 2 for a level 2 cache.

- reg : Physical base address and size of cache controller's memory mapped

  registers.

Optional properties:

- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of

  read, write and setup latencies. Minimum valid values are 1. Controllers

  without setup latency control should use a value of 0.

- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of

  read, write and setup latencies. Controllers without setup latency control

  should use 0. Controllers without separate read and write Tag RAM latency

  values should only use the first cell.

- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.

- arm,filter-ranges : <start length> Starting address and length of window to

  filter. Addresses in the filter window are directed to the M1 port. Other

  addresses will go to the M0 port.

- interrupts : 1 combined interrupt.

Example:

L2: cache-controller {

        compatible = "arm,pl310-cache";

        reg = <0xfff12000 0x1000>;

        arm,data-latency = <1 1 1>;

        arm,tag-latency = <2 2 2>;

        arm,filter-latency = <0x80000000 0x8000000>;

        cache-unified;

        cache-level = <2>;

	interrupts = <45>;

};

the devices explicitly. Please see Documentation/i2c/instantiating-devices for

details.

WARNING: Do not access chip registers using the i2cdump command, and do not use

any of the i2ctools commands on a command register (0xa5 to 0xac). The chips

supported by this driver interpret any access to a command register (including

read commands) as request to execute the command in question. This may result in

power loss, board resets, and/or Flash corruption. Worst case, your board may

turn into a brick.

Sysfs entries

-------------

#define L2X0_CLEAN_INV_LINE_PA		0x7F0

#define L2X0_CLEAN_INV_LINE_IDX		0x7F8

#define L2X0_CLEAN_INV_WAY		0x7FC

#define L2X0_LOCKDOWN_WAY_D		0x900

#define L2X0_LOCKDOWN_WAY_I		0x904

/*

 * The lockdown registers repeat 8 times for L310, the L210 has only one

 * D and one I lockdown register at 0x0900 and 0x0904.

 */

#define L2X0_LOCKDOWN_WAY_D_BASE	0x900

#define L2X0_LOCKDOWN_WAY_I_BASE	0x904

#define L2X0_LOCKDOWN_STRIDE		0x08

#define L2X0_ADDR_FILTER_START		0xC00

#define L2X0_ADDR_FILTER_END		0xC04

#define L2X0_TEST_OPERATION		0xF00

#define L2X0_LINE_DATA			0xF10

#define L2X0_LINE_TAG			0xF30

#define L2X0_CACHE_ID_PART_MASK		(0xf << 6)

#define L2X0_CACHE_ID_PART_L210		(1 << 6)

#define L2X0_CACHE_ID_PART_L310		(3 << 6)

#define L2X0_CACHE_ID_RTL_MASK          0x3f

#define L2X0_CACHE_ID_RTL_R0P0          0x0

#define L2X0_CACHE_ID_RTL_R1P0          0x2

#define L2X0_CACHE_ID_RTL_R2P0          0x4

#define L2X0_CACHE_ID_RTL_R3P0          0x5

#define L2X0_CACHE_ID_RTL_R3P1          0x6

#define L2X0_CACHE_ID_RTL_R3P2          0x8

#define L2X0_AUX_CTRL_MASK			0xc0000fff

#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT	0

#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK	0x7

#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT	3

#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK	(0x7 << 3)

#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT		6

#define L2X0_AUX_CTRL_TAG_LATENCY_MASK		(0x7 << 6)

#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT	9

#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK	(0x7 << 9)

#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT	16

#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT		17

#define L2X0_AUX_CTRL_WAY_SIZE_MASK		(0x7 << 17)

#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT	29

#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT		30

#define L2X0_LATENCY_CTRL_SETUP_SHIFT	0

#define L2X0_LATENCY_CTRL_RD_SHIFT	4

#define L2X0_LATENCY_CTRL_WR_SHIFT	8

#define L2X0_ADDR_FILTER_EN		1

#ifndef __ASSEMBLY__

extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);

extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);

struct l2x0_regs {

	unsigned long phy_base;

	unsigned long aux_ctrl;

	/*

	 * Whether the following registers need to be saved/restored

	 * depends on platform

	 */

	unsigned long tag_latency;

	unsigned long data_latency;

	unsigned long filter_start;

	unsigned long filter_end;

	unsigned long prefetch_ctrl;

	unsigned long pwr_ctrl;

};

extern struct l2x0_regs l2x0_saved_regs;

#endif

#endif

	void (*sync)(void);

#endif

	void (*set_debug)(unsigned long);

	void (*resume)(void);

};

#ifdef CONFIG_OUTER_CACHE

		outer_cache.disable();

}

static inline void outer_resume(void)

{

	if (outer_cache.resume)

		outer_cache.resume();

}

#else

static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)

#include <asm/thread_info.h>

#include <asm/memory.h>

#include <asm/procinfo.h>

#include <asm/hardware/cache-l2x0.h>

#include <linux/kbuild.h>

/*

  DEFINE(S_OLD_R0,		offsetof(struct pt_regs, ARM_ORIG_r0));

  DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));

  BLANK();

#ifdef CONFIG_CACHE_L2X0

  DEFINE(L2X0_R_PHY_BASE,	offsetof(struct l2x0_regs, phy_base));

  DEFINE(L2X0_R_AUX_CTRL,	offsetof(struct l2x0_regs, aux_ctrl));

  DEFINE(L2X0_R_TAG_LATENCY,	offsetof(struct l2x0_regs, tag_latency));

  DEFINE(L2X0_R_DATA_LATENCY,	offsetof(struct l2x0_regs, data_latency));

  DEFINE(L2X0_R_FILTER_START,	offsetof(struct l2x0_regs, filter_start));

  DEFINE(L2X0_R_FILTER_END,	offsetof(struct l2x0_regs, filter_end));

  DEFINE(L2X0_R_PREFETCH_CTRL,	offsetof(struct l2x0_regs, prefetch_ctrl));

  DEFINE(L2X0_R_PWR_CTRL,	offsetof(struct l2x0_regs, pwr_ctrl));

  BLANK();

#endif

#ifdef CONFIG_CPU_HAS_ASID

  DEFINE(MM_CONTEXT_ID,		offsetof(struct mm_struct, context.id));

  BLANK();