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Commit 1e0b1a0c authored by James Morse's avatar James Morse Committed by Sami Tolvanen
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UPSTREAM: arm64: add ARMv8.2 id_aa64mmfr2 boiler plate 



ARMv8.2 adds a new feature register id_aa64mmfr2. This patch adds the
cpu feature boiler plate used by the actual features in later patches.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>

Bug: 31432001
Change-Id: Ie459bb5936c53378e9b1919795905601cc8e131a
(cherry picked from commit 406e308770a92bd33995b2e5b681e86358328bb0)
Signed-off-by: default avatarSami Tolvanen <samitolvanen@google.com>
parent 62c94444

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ struct cpuinfo_arm64 { 
	u64		reg_id_aa64isar1;

	u64		reg_id_aa64mmfr0;

	u64		reg_id_aa64mmfr1;

	u64		reg_id_aa64mmfr2;

	u64		reg_id_aa64pfr0;

	u64		reg_id_aa64pfr1;

arch/arm64/include/asm/sysreg.h

+4 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ 


#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)

#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)

#define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)



#define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)

#define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
@@ -135,6 +136,9 @@ 
#define ID_AA64MMFR1_VMIDBITS_SHIFT	4

#define ID_AA64MMFR1_HADBS_SHIFT	0



/* id_aa64mmfr2 */

#define ID_AA64MMFR2_UAO_SHIFT		4



/* id_aa64dfr0 */

#define ID_AA64DFR0_CTX_CMPS_SHIFT	28

#define ID_AA64DFR0_WRPS_SHIFT		20

arch/arm64/kernel/cpufeature.c

+10 −0
Original line number Diff line number Diff line
@@ -122,6 +122,11 @@ static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 
	ARM64_FTR_END,

};



static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static struct arm64_ftr_bits ftr_ctr[] = {

	U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),	/* RAO */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
@@ -283,6 +288,7 @@ static struct arm64_ftr_reg arm64_ftr_regs[] = { 
	/* Op1 = 0, CRn = 0, CRm = 7 */

	ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),

	ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),

	ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),



	/* Op1 = 3, CRn = 0, CRm = 0 */

	ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
@@ -407,6 +413,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) 
	init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);

	init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);

	init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);

	init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
@@ -516,6 +523,8 @@ void update_cpu_features(int cpu, 
				      info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);

	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,

				      info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);

	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,

				      info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);



	/*

	 * EL3 is not our concern.
@@ -785,6 +794,7 @@ static u64 __raw_read_system_reg(u32 sys_id) 
	case SYS_ID_AA64DFR1_EL1:	return read_cpuid(SYS_ID_AA64DFR0_EL1);

	case SYS_ID_AA64MMFR0_EL1:	return read_cpuid(SYS_ID_AA64MMFR0_EL1);

	case SYS_ID_AA64MMFR1_EL1:	return read_cpuid(SYS_ID_AA64MMFR1_EL1);

	case SYS_ID_AA64MMFR2_EL1:	return read_cpuid(SYS_ID_AA64MMFR2_EL1);

	case SYS_ID_AA64ISAR0_EL1:	return read_cpuid(SYS_ID_AA64ISAR0_EL1);

	case SYS_ID_AA64ISAR1_EL1:	return read_cpuid(SYS_ID_AA64ISAR1_EL1);

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -205,6 +205,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
	info->reg_id_aa64isar1 = read_cpuid(SYS_ID_AA64ISAR1_EL1);

	info->reg_id_aa64mmfr0 = read_cpuid(SYS_ID_AA64MMFR0_EL1);

	info->reg_id_aa64mmfr1 = read_cpuid(SYS_ID_AA64MMFR1_EL1);

	info->reg_id_aa64mmfr2 = read_cpuid(SYS_ID_AA64MMFR2_EL1);

	info->reg_id_aa64pfr0 = read_cpuid(SYS_ID_AA64PFR0_EL1);

	info->reg_id_aa64pfr1 = read_cpuid(SYS_ID_AA64PFR1_EL1);