Merge branch 'hwmod_clockevent_2.6.39' of git://git.pwsan.com/linux-2.6 into omap-for-linus (1d90da95) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/mach-omap2/omap_hwmod.c

+100 −54

Original line number	Diff line number	Diff line
		/*
		* omap_hwmod implementation for OMAP2/3/4
		*
		* Copyright (C) 2009-2010 Nokia Corporation
		* Copyright (C) 2009-2011 Nokia Corporation
		*
		* Paul Walmsley, Benoît Cousson, Kevin Hilman
		*
		@@ -162,9 +162,6 @@ static LIST_HEAD(omap_hwmod_list);
		/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
		static struct omap_hwmod *mpu_oh;

		/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */
		static u8 inited;


		/* Private functions */

		@@ -904,18 +901,16 @@ static struct omap_hwmod _lookup(const char name)
		* @oh: struct omap_hwmod *
		* @data: not used; pass NULL
		*
		* Called by omap_hwmod_late_init() (after omap2_clk_init()).
		* Resolves all clock names embedded in the hwmod. Returns -EINVAL if
		* the omap_hwmod has not yet been registered or if the clocks have
		* already been initialized, 0 on success, or a non-zero error on
		* failure.
		* Called by omap_hwmod_setup_*() (after omap2_clk_init()).
		* Resolves all clock names embedded in the hwmod. Returns 0 on
		* success, or a negative error code on failure.
		*/
		static int _init_clocks(struct omap_hwmod oh, void data)
		{
		int ret = 0;

		if (!oh \|\| (oh->_state != _HWMOD_STATE_REGISTERED))
		return -EINVAL;
		if (oh->_state != _HWMOD_STATE_REGISTERED)
		return 0;

		pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);

		@@ -1354,14 +1349,16 @@ static int _shutdown(struct omap_hwmod *oh)
		* @oh: struct omap_hwmod *
		*
		* Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
		* OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the
		* wrong state or returns 0.
		* OCP_SYSCONFIG register. Returns 0.
		*/
		static int _setup(struct omap_hwmod oh, void data)
		{
		int i, r;
		u8 postsetup_state;

		if (oh->_state != _HWMOD_STATE_CLKS_INITED)
		return 0;

		/* Set iclk autoidle mode */
		if (oh->slaves_cnt > 0) {
		for (i = 0; i < oh->slaves_cnt; i++) {
		@@ -1455,7 +1452,7 @@ static int _setup(struct omap_hwmod oh, void data)
		*/
		static int __init _register(struct omap_hwmod *oh)
		{
		int ret, ms_id;
		int ms_id;

		if (!oh \|\| !oh->name \|\| !oh->class \|\| !oh->class->name \|\|
		(oh->_state != _HWMOD_STATE_UNKNOWN))
		@@ -1478,9 +1475,14 @@ static int __init _register(struct omap_hwmod *oh)

		oh->_state = _HWMOD_STATE_REGISTERED;

		ret = 0;
		/*
		* XXX Rather than doing a strcmp(), this should test a flag
		* set in the hwmod data, inserted by the autogenerator code.
		*/
		if (!strcmp(oh->name, MPU_INITIATOR_NAME))
		mpu_oh = oh;

		return ret;
		return 0;
		}


		@@ -1583,38 +1585,30 @@ int omap_hwmod_for_each(int (fn)(struct omap_hwmod oh, void *data),
		return ret;
		}


		/**
		* omap_hwmod_init - init omap_hwmod code and register hwmods
		* omap_hwmod_register - register an array of hwmods
		* @ohs: pointer to an array of omap_hwmods to register
		*
		* Intended to be called early in boot before the clock framework is
		* initialized. If @ohs is not null, will register all omap_hwmods
		* listed in @ohs that are valid for this chip. Returns -EINVAL if
		* omap_hwmod_init() has already been called or 0 otherwise.
		* listed in @ohs that are valid for this chip. Returns 0.
		*/
		int __init omap_hwmod_init(struct omap_hwmod **ohs)
		int __init omap_hwmod_register(struct omap_hwmod **ohs)
		{
		struct omap_hwmod *oh;
		int r;

		if (inited)
		return -EINVAL;

		inited = 1;
		int r, i;

		if (!ohs)
		return 0;

		oh = *ohs;
		while (oh) {
		if (omap_chip_is(oh->omap_chip)) {
		r = _register(oh);
		WARN(r, "omap_hwmod: %s: _register returned "
		"%d\n", oh->name, r);
		}
		oh = *++ohs;
		}
		i = 0;
		do {
		if (!omap_chip_is(ohs[i]->omap_chip))
		continue;

		r = _register(ohs[i]);
		WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
		r);
		} while (ohs[++i]);

		return 0;
		}
		@@ -1622,12 +1616,14 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs)
		/*
		* _populate_mpu_rt_base - populate the virtual address for a hwmod
		*
		* Must be called only from omap_hwmod_late_init so ioremap works properly.
		* Must be called only from omap_hwmod_setup_*() so ioremap works properly.
		* Assumes the caller takes care of locking if needed.
		*
		*/
		static int __init _populate_mpu_rt_base(struct omap_hwmod oh, void data)
		{
		if (oh->_state != _HWMOD_STATE_REGISTERED)
		return 0;

		if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
		return 0;

		@@ -1640,31 +1636,81 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod oh, void data)
		}

		/**
		* omap_hwmod_late_init - do some post-clock framework initialization
		* omap_hwmod_setup_one - set up a single hwmod
		* @oh_name: const char * name of the already-registered hwmod to set up
		*
		* Must be called after omap2_clk_init(). Resolves the struct clk
		* names to struct clk pointers for each registered omap_hwmod. Also
		* calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon
		* success.
		*/
		int __init omap_hwmod_setup_one(const char *oh_name)
		{
		struct omap_hwmod *oh;
		int r;

		pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);

		if (!mpu_oh) {
		pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
		oh_name, MPU_INITIATOR_NAME);
		return -EINVAL;
		}

		oh = _lookup(oh_name);
		if (!oh) {
		WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
		return -EINVAL;
		}

		if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
		omap_hwmod_setup_one(MPU_INITIATOR_NAME);

		r = _populate_mpu_rt_base(oh, NULL);
		if (IS_ERR_VALUE(r)) {
		WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
		return -EINVAL;
		}

		r = _init_clocks(oh, NULL);
		if (IS_ERR_VALUE(r)) {
		WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
		return -EINVAL;
		}

		_setup(oh, NULL);

		return 0;
		}

		/**
		* omap_hwmod_setup - do some post-clock framework initialization
		*
		* Must be called after omap2_clk_init(). Resolves the struct clk names
		* to struct clk pointers for each registered omap_hwmod. Also calls
		* _setup() on each hwmod. Returns 0.
		* _setup() on each hwmod. Returns 0 upon success.
		*/
		static int __init omap_hwmod_late_init(void)
		static int __init omap_hwmod_setup_all(void)
		{
		int r;

		if (!mpu_oh) {
		pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
		__func__, MPU_INITIATOR_NAME);
		return -EINVAL;
		}

		r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);

		/* XXX check return value */
		r = omap_hwmod_for_each(_init_clocks, NULL);
		WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n");

		mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
		WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
		MPU_INITIATOR_NAME);
		WARN(IS_ERR_VALUE(r),
		"omap_hwmod: %s: _init_clocks failed\n", __func__);

		omap_hwmod_for_each(_setup, NULL);

		return 0;
		}
		core_initcall(omap_hwmod_late_init);
		core_initcall(omap_hwmod_setup_all);

		/**
		* omap_hwmod_enable - enable an omap_hwmod
		@@ -2183,11 +2229,11 @@ int omap_hwmod_for_each_by_class(const char *classname,
		* @oh: struct omap_hwmod *
		* @state: state that _setup() should leave the hwmod in
		*
		* Sets the hwmod state that @oh will enter at the end of _setup() (called by
		* omap_hwmod_late_init()). Only valid to call between calls to
		* omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or
		* -EINVAL if there is a problem with the arguments or if the hwmod is
		* in the wrong state.
		* Sets the hwmod state that @oh will enter at the end of _setup()
		* (called by omap_hwmod_setup_*()). Only valid to call between
		* calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns
		* 0 upon success or -EINVAL if there is a problem with the arguments
		* or if the hwmod is in the wrong state.
		*/
		int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
		{

arch/arm/mach-omap2/omap_hwmod_2420_data.c

+635 −1

Original line number	Diff line number	Diff line
		@@ -19,6 +19,7 @@
		#include <plat/i2c.h>
		#include <plat/gpio.h>
		#include <plat/mcspi.h>
		#include <plat/dmtimer.h>
		#include <plat/l3_2xxx.h>
		#include <plat/l4_2xxx.h>

		@@ -337,6 +338,625 @@ static struct omap_hwmod omap2420_iva_hwmod = {
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* Timer Common */
		static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
		.rev_offs = 0x0000,
		.sysc_offs = 0x0010,
		.syss_offs = 0x0014,
		.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_CLOCKACTIVITY \|
		SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
		SYSC_HAS_AUTOIDLE),
		.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
		.sysc_fields = &omap_hwmod_sysc_type1,
		};

		static struct omap_hwmod_class omap2420_timer_hwmod_class = {
		.name = "timer",
		.sysc = &omap2420_timer_sysc,
		.rev = OMAP_TIMER_IP_VERSION_1,
		};

		/* timer1 */
		static struct omap_hwmod omap2420_timer1_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
		{ .irq = 37, },
		};

		static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
		{
		.pa_start = 0x48028000,
		.pa_end = 0x48028000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_wkup -> timer1 */
		static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
		.master = &omap2420_l4_wkup_hwmod,
		.slave = &omap2420_timer1_hwmod,
		.clk = "gpt1_ick",
		.addr = omap2420_timer1_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer1 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
		&omap2420_l4_wkup__timer1,
		};

		/* timer1 hwmod */
		static struct omap_hwmod omap2420_timer1_hwmod = {
		.name = "timer1",
		.mpu_irqs = omap2420_timer1_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
		.main_clk = "gpt1_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT1_SHIFT,
		.module_offs = WKUP_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
		},
		},
		.slaves = omap2420_timer1_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer2 */
		static struct omap_hwmod omap2420_timer2_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
		{ .irq = 38, },
		};

		static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
		{
		.pa_start = 0x4802a000,
		.pa_end = 0x4802a000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer2 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer2_hwmod,
		.clk = "gpt2_ick",
		.addr = omap2420_timer2_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer2 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
		&omap2420_l4_core__timer2,
		};

		/* timer2 hwmod */
		static struct omap_hwmod omap2420_timer2_hwmod = {
		.name = "timer2",
		.mpu_irqs = omap2420_timer2_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
		.main_clk = "gpt2_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT2_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
		},
		},
		.slaves = omap2420_timer2_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer3 */
		static struct omap_hwmod omap2420_timer3_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
		{ .irq = 39, },
		};

		static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
		{
		.pa_start = 0x48078000,
		.pa_end = 0x48078000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer3 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer3_hwmod,
		.clk = "gpt3_ick",
		.addr = omap2420_timer3_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer3 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
		&omap2420_l4_core__timer3,
		};

		/* timer3 hwmod */
		static struct omap_hwmod omap2420_timer3_hwmod = {
		.name = "timer3",
		.mpu_irqs = omap2420_timer3_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
		.main_clk = "gpt3_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT3_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
		},
		},
		.slaves = omap2420_timer3_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer4 */
		static struct omap_hwmod omap2420_timer4_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
		{ .irq = 40, },
		};

		static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
		{
		.pa_start = 0x4807a000,
		.pa_end = 0x4807a000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer4 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer4_hwmod,
		.clk = "gpt4_ick",
		.addr = omap2420_timer4_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer4 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
		&omap2420_l4_core__timer4,
		};

		/* timer4 hwmod */
		static struct omap_hwmod omap2420_timer4_hwmod = {
		.name = "timer4",
		.mpu_irqs = omap2420_timer4_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
		.main_clk = "gpt4_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT4_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
		},
		},
		.slaves = omap2420_timer4_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer5 */
		static struct omap_hwmod omap2420_timer5_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
		{ .irq = 41, },
		};

		static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
		{
		.pa_start = 0x4807c000,
		.pa_end = 0x4807c000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer5 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer5_hwmod,
		.clk = "gpt5_ick",
		.addr = omap2420_timer5_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer5 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
		&omap2420_l4_core__timer5,
		};

		/* timer5 hwmod */
		static struct omap_hwmod omap2420_timer5_hwmod = {
		.name = "timer5",
		.mpu_irqs = omap2420_timer5_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
		.main_clk = "gpt5_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT5_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
		},
		},
		.slaves = omap2420_timer5_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};


		/* timer6 */
		static struct omap_hwmod omap2420_timer6_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
		{ .irq = 42, },
		};

		static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
		{
		.pa_start = 0x4807e000,
		.pa_end = 0x4807e000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer6 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer6_hwmod,
		.clk = "gpt6_ick",
		.addr = omap2420_timer6_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer6 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
		&omap2420_l4_core__timer6,
		};

		/* timer6 hwmod */
		static struct omap_hwmod omap2420_timer6_hwmod = {
		.name = "timer6",
		.mpu_irqs = omap2420_timer6_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
		.main_clk = "gpt6_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT6_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
		},
		},
		.slaves = omap2420_timer6_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer7 */
		static struct omap_hwmod omap2420_timer7_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
		{ .irq = 43, },
		};

		static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
		{
		.pa_start = 0x48080000,
		.pa_end = 0x48080000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer7 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer7_hwmod,
		.clk = "gpt7_ick",
		.addr = omap2420_timer7_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer7 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
		&omap2420_l4_core__timer7,
		};

		/* timer7 hwmod */
		static struct omap_hwmod omap2420_timer7_hwmod = {
		.name = "timer7",
		.mpu_irqs = omap2420_timer7_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
		.main_clk = "gpt7_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT7_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
		},
		},
		.slaves = omap2420_timer7_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer8 */
		static struct omap_hwmod omap2420_timer8_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
		{ .irq = 44, },
		};

		static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
		{
		.pa_start = 0x48082000,
		.pa_end = 0x48082000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer8 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer8_hwmod,
		.clk = "gpt8_ick",
		.addr = omap2420_timer8_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer8 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
		&omap2420_l4_core__timer8,
		};

		/* timer8 hwmod */
		static struct omap_hwmod omap2420_timer8_hwmod = {
		.name = "timer8",
		.mpu_irqs = omap2420_timer8_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
		.main_clk = "gpt8_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT8_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
		},
		},
		.slaves = omap2420_timer8_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer9 */
		static struct omap_hwmod omap2420_timer9_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
		{ .irq = 45, },
		};

		static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
		{
		.pa_start = 0x48084000,
		.pa_end = 0x48084000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer9 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer9_hwmod,
		.clk = "gpt9_ick",
		.addr = omap2420_timer9_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer9 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
		&omap2420_l4_core__timer9,
		};

		/* timer9 hwmod */
		static struct omap_hwmod omap2420_timer9_hwmod = {
		.name = "timer9",
		.mpu_irqs = omap2420_timer9_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
		.main_clk = "gpt9_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT9_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
		},
		},
		.slaves = omap2420_timer9_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer10 */
		static struct omap_hwmod omap2420_timer10_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
		{ .irq = 46, },
		};

		static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
		{
		.pa_start = 0x48086000,
		.pa_end = 0x48086000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer10 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer10_hwmod,
		.clk = "gpt10_ick",
		.addr = omap2420_timer10_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer10 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
		&omap2420_l4_core__timer10,
		};

		/* timer10 hwmod */
		static struct omap_hwmod omap2420_timer10_hwmod = {
		.name = "timer10",
		.mpu_irqs = omap2420_timer10_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
		.main_clk = "gpt10_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT10_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
		},
		},
		.slaves = omap2420_timer10_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer11 */
		static struct omap_hwmod omap2420_timer11_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
		{ .irq = 47, },
		};

		static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
		{
		.pa_start = 0x48088000,
		.pa_end = 0x48088000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer11 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer11_hwmod,
		.clk = "gpt11_ick",
		.addr = omap2420_timer11_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer11 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
		&omap2420_l4_core__timer11,
		};

		/* timer11 hwmod */
		static struct omap_hwmod omap2420_timer11_hwmod = {
		.name = "timer11",
		.mpu_irqs = omap2420_timer11_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
		.main_clk = "gpt11_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT11_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
		},
		},
		.slaves = omap2420_timer11_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* timer12 */
		static struct omap_hwmod omap2420_timer12_hwmod;
		static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
		{ .irq = 48, },
		};

		static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
		{
		.pa_start = 0x4808a000,
		.pa_end = 0x4808a000 + SZ_1K - 1,
		.flags = ADDR_TYPE_RT
		},
		};

		/* l4_core -> timer12 */
		static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
		.master = &omap2420_l4_core_hwmod,
		.slave = &omap2420_timer12_hwmod,
		.clk = "gpt12_ick",
		.addr = omap2420_timer12_addrs,
		.addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* timer12 slave port */
		static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
		&omap2420_l4_core__timer12,
		};

		/* timer12 hwmod */
		static struct omap_hwmod omap2420_timer12_hwmod = {
		.name = "timer12",
		.mpu_irqs = omap2420_timer12_mpu_irqs,
		.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
		.main_clk = "gpt12_fck",
		.prcm = {
		.omap2 = {
		.prcm_reg_id = 1,
		.module_bit = OMAP24XX_EN_GPT12_SHIFT,
		.module_offs = CORE_MOD,
		.idlest_reg_id = 1,
		.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
		},
		},
		.slaves = omap2420_timer12_slaves,
		.slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
		.class = &omap2420_timer_hwmod_class,
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
		};

		/* l4_wkup -> wd_timer2 */
		static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
		{
		@@ -1326,6 +1946,20 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
		&omap2420_l4_wkup_hwmod,
		&omap2420_mpu_hwmod,
		&omap2420_iva_hwmod,

		&omap2420_timer1_hwmod,
		&omap2420_timer2_hwmod,
		&omap2420_timer3_hwmod,
		&omap2420_timer4_hwmod,
		&omap2420_timer5_hwmod,
		&omap2420_timer6_hwmod,
		&omap2420_timer7_hwmod,
		&omap2420_timer8_hwmod,
		&omap2420_timer9_hwmod,
		&omap2420_timer10_hwmod,
		&omap2420_timer11_hwmod,
		&omap2420_timer12_hwmod,

		&omap2420_wd_timer2_hwmod,
		&omap2420_uart1_hwmod,
		&omap2420_uart2_hwmod,
		@@ -1356,5 +1990,5 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {

		int __init omap2420_hwmod_init(void)
		{
		return omap_hwmod_init(omap2420_hwmods);
		return omap_hwmod_register(omap2420_hwmods);
		}

arch/arm/mach-omap2/omap_hwmod_2430_data.c

+634 −1

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arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

+650 −1

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arch/arm/mach-omap2/omap_hwmod_44xx_data.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -5125,6 +5125,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {

		int __init omap44xx_hwmod_init(void)
		{
		return omap_hwmod_init(omap44xx_hwmods);
		return omap_hwmod_register(omap44xx_hwmods);
		}