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Commit 1ce9a2da authored by Aditya Bavanari's avatar Aditya Bavanari
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ASoC: msm: Update MUX register configuration for PRI TDM 



Update the MUX register configuration for Primary TDM.
LPASS_CSR_GP_IO_MUX_SEC_TLMM_CTL is not required to be
set for the Primary TDM routing.

Change-Id: I04724ed5e2a39f75874f1a73be7ab6719f12d4fc
Signed-off-by: default avatarAditya Bavanari <abavanar@codeaurora.org>
parent ac8bbe8c

sound/soc/msm/msm8952-slimbus.c

+0 −8
Original line number Diff line number Diff line
@@ -2750,14 +2750,6 @@ int msm_tdm_startup(struct snd_pcm_substream *substream) 
			return -EINVAL;

		}



		if (pdata->vaddr_gpio_mux_sec_tlmm_ctl) {

			val = ioread32(pdata->vaddr_gpio_mux_sec_tlmm_ctl);

			val = val | 0x00000002;

			iowrite32(val, pdata->vaddr_gpio_mux_sec_tlmm_ctl);

		} else {

			return -EINVAL;

		}



		if (pdata->vaddr_gpio_mux_mic_ctl) {

			val = ioread32(pdata->vaddr_gpio_mux_mic_ctl);

			val = val | 0x00000002;