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Commit 1c8c38c5 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
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drm/i915: Disable AsyncFlip performance optimisations 

This is a required workarounds for all products, especially on gen6+
where it causes the command streamer to fail to parse instructions
following a WAIT_FOR_EVENT. We use WAIT_FOR_EVENT for synchronising
between the GPU and the display engines, and so this bit being unset may
cause hangs.

References: https://bugzilla.kernel.org/show_bug.cgi?id=52311


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 014b3440

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -533,6 +533,7 @@ 
#define MI_MODE		0x0209c

#define MI_MODE		0x0209c

# define VS_TIMER_DISPATCH				(1 << 6)

# define VS_TIMER_DISPATCH				(1 << 6)

# define MI_FLUSH_ENABLE				(1 << 12)

# define MI_FLUSH_ENABLE				(1 << 12)

# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)





#define GEN6_GT_MODE	0x20d0

#define GEN6_GT_MODE	0x20d0

#define   GEN6_GT_MODE_HI				(1 << 9)

#define   GEN6_GT_MODE_HI				(1 << 9)

drivers/gpu/drm/i915/intel_ringbuffer.c

+13 −6
Original line number Original line Diff line number Diff line
@@ -505,13 +505,20 @@ static int init_render_ring(struct intel_ring_buffer *ring) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret = init_ring_common(ring);

	int ret = init_ring_common(ring);





	if (INTEL_INFO(dev)->gen > 3) {

	if (INTEL_INFO(dev)->gen > 3)

		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));

		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));



	/* We need to disable the AsyncFlip performance optimisations in order

	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be

	 * programmed to '1' on all products.

	 */

	if (INTEL_INFO(dev)->gen >= 6)

		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));



	if (IS_GEN7(dev))

	if (IS_GEN7(dev))

		I915_WRITE(GFX_MODE_GEN7,

		I915_WRITE(GFX_MODE_GEN7,

			   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |

			   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |

			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));

			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));

	}





	if (INTEL_INFO(dev)->gen >= 5) {

	if (INTEL_INFO(dev)->gen >= 5) {

		ret = init_pipe_control(ring);

		ret = init_pipe_control(ring);