Loading drivers/soc/qcom/scm.c +9 −4 Original line number Diff line number Diff line Loading @@ -108,6 +108,7 @@ struct scm_response { #define R3_STR "x3" #define R4_STR "x4" #define R5_STR "x5" #define R6_STR "x6" /* Outer caches unsupported on ARM64 platforms */ #define outer_inv_range(x, y) Loading Loading @@ -377,6 +378,7 @@ static int __scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, register u64 r3 asm("r3") = x3; register u64 r4 asm("r4") = x4; register u64 r5 asm("r5") = x5; register u64 r6 asm("r6") = 0; do { asm volatile( Loading @@ -390,14 +392,15 @@ static int __scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, __asmeq("%7", R3_STR) __asmeq("%8", R4_STR) __asmeq("%9", R5_STR) __asmeq("%10", R6_STR) #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0\n" : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), "r" (r5) : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "r" (r5), "r" (r6) : "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); } while (r0 == SCM_INTERRUPTED); Loading @@ -420,6 +423,7 @@ static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, register u32 r3 asm("r3") = w3; register u32 r4 asm("r4") = w4; register u32 r5 asm("r5") = w5; register u32 r6 asm("r6") = 0; do { asm volatile( Loading @@ -433,14 +437,15 @@ static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, __asmeq("%7", R3_STR) __asmeq("%8", R4_STR) __asmeq("%9", R5_STR) __asmeq("%10", R6_STR) #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0\n" : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), "r" (r5) : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "r" (r5), "r" (r6) : "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); } while (r0 == SCM_INTERRUPTED); Loading Loading
drivers/soc/qcom/scm.c +9 −4 Original line number Diff line number Diff line Loading @@ -108,6 +108,7 @@ struct scm_response { #define R3_STR "x3" #define R4_STR "x4" #define R5_STR "x5" #define R6_STR "x6" /* Outer caches unsupported on ARM64 platforms */ #define outer_inv_range(x, y) Loading Loading @@ -377,6 +378,7 @@ static int __scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, register u64 r3 asm("r3") = x3; register u64 r4 asm("r4") = x4; register u64 r5 asm("r5") = x5; register u64 r6 asm("r6") = 0; do { asm volatile( Loading @@ -390,14 +392,15 @@ static int __scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5, __asmeq("%7", R3_STR) __asmeq("%8", R4_STR) __asmeq("%9", R5_STR) __asmeq("%10", R6_STR) #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0\n" : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), "r" (r5) : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "r" (r5), "r" (r6) : "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); } while (r0 == SCM_INTERRUPTED); Loading @@ -420,6 +423,7 @@ static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, register u32 r3 asm("r3") = w3; register u32 r4 asm("r4") = w4; register u32 r5 asm("r5") = w5; register u32 r6 asm("r6") = 0; do { asm volatile( Loading @@ -433,14 +437,15 @@ static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, __asmeq("%7", R3_STR) __asmeq("%8", R4_STR) __asmeq("%9", R5_STR) __asmeq("%10", R6_STR) #ifdef REQUIRES_SEC ".arch_extension sec\n" #endif "smc #0\n" : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), "r" (r5) : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "r" (r5), "r" (r6) : "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); } while (r0 == SCM_INTERRUPTED); Loading