Loading drivers/gpu/msm/adreno_a3xx.c +2 −1 Original line number Diff line number Diff line Loading @@ -751,6 +751,7 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit) (1 << A3XX_INT_CP_IB1_INT) | \ (1 << A3XX_INT_CP_IB2_INT) | \ (1 << A3XX_INT_CP_RB_INT) | \ (1 << A3XX_INT_CACHE_FLUSH_TS) | \ (1 << A3XX_INT_CP_REG_PROTECT_FAULT) | \ (1 << A3XX_INT_CP_AHB_ERROR_HALT) | \ (1 << A3XX_INT_UCHE_OOB_ACCESS)) Loading Loading @@ -778,7 +779,7 @@ static struct adreno_irq_funcs a3xx_irq_funcs[] = { ADRENO_IRQ_CALLBACK(NULL), /* 17 - CP_RB_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 18 - CP_VS_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 19 - CP_PS_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 20 - CP_CACHE_FLUSH_TS */ ADRENO_IRQ_CALLBACK(adreno_cp_callback), /* 20 - CP_CACHE_FLUSH_TS */ /* 21 - CP_AHB_ERROR_FAULT */ ADRENO_IRQ_CALLBACK(a3xx_err_callback), ADRENO_IRQ_CALLBACK(NULL), /* 22 - Unused */ Loading drivers/gpu/msm/adreno_a4xx.c +2 −1 Original line number Diff line number Diff line Loading @@ -1719,6 +1719,7 @@ static struct adreno_coresight a4xx_coresight = { (1 << A4XX_INT_CP_IB1_INT) | \ (1 << A4XX_INT_CP_IB2_INT) | \ (1 << A4XX_INT_CP_RB_INT) | \ (1 << A4XX_INT_CACHE_FLUSH_TS) | \ (1 << A4XX_INT_CP_REG_PROTECT_FAULT) | \ (1 << A4XX_INT_CP_AHB_ERROR_HALT) | \ (1 << A4XX_INT_RBBM_ATB_BUS_OVERFLOW) | \ Loading Loading @@ -1755,7 +1756,7 @@ static struct adreno_irq_funcs a4xx_irq_funcs[] = { ADRENO_IRQ_CALLBACK(NULL), /* 17 - CP_RB_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 18 - CP_VS_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 19 - CP_PS_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 20 - CP_CACHE_FLUSH_TS */ ADRENO_IRQ_CALLBACK(adreno_cp_callback), /* 20 - CP_CACHE_FLUSH_TS */ /* 21 - CP_AHB_ERROR_FAULT */ ADRENO_IRQ_CALLBACK(a4xx_err_callback), ADRENO_IRQ_CALLBACK(a4xx_err_callback), /* 22 - RBBM_ATB_BUS_OVERFLOW */ Loading drivers/gpu/msm/adreno_a5xx.c +2 −1 Original line number Diff line number Diff line Loading @@ -2790,6 +2790,7 @@ static void a5xx_gpmu_int_callback(struct adreno_device *adreno_dev, int bit) (1 << A5XX_INT_CP_IB1) | \ (1 << A5XX_INT_CP_IB2) | \ (1 << A5XX_INT_CP_RB) | \ (1 << A5XX_INT_CP_CACHE_FLUSH_TS) | \ (1 << A5XX_INT_RBBM_ATB_BUS_OVERFLOW) | \ (1 << A5XX_INT_UCHE_OOB_ACCESS) | \ (1 << A5XX_INT_UCHE_TRAP_INTR) | \ Loading Loading @@ -2826,7 +2827,7 @@ static struct adreno_irq_funcs a5xx_irq_funcs[] = { ADRENO_IRQ_CALLBACK(NULL), /* 17 - CP_RB_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 18 - CP_WT_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 19 - UNKNOWN_1 */ ADRENO_IRQ_CALLBACK(NULL), /* 20 - CP_CACHE_FLUSH_TS */ ADRENO_IRQ_CALLBACK(adreno_cp_callback), /* 20 - CP_CACHE_FLUSH_TS */ /* 21 - UNUSED_2 */ ADRENO_IRQ_CALLBACK(NULL), ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 22 - RBBM_ATB_BUS_OVERFLOW */ Loading drivers/gpu/msm/adreno_ringbuffer.c +4 −10 Original line number Diff line number Diff line Loading @@ -565,10 +565,6 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb, total_sizedwords += (secured_ctxt) ? 26 : 0; /* Add two dwords for the CP_INTERRUPT */ total_sizedwords += (drawctxt || (flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) ? 2 : 0; /* context rollover */ if (adreno_is_a3xx(adreno_dev)) total_sizedwords += 3; Loading Loading @@ -707,6 +703,9 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb, * set and hence the rb timestamp will be used in else statement below. */ *ringcmds++ = cp_mem_packet(adreno_dev, CP_EVENT_WRITE, 3, 1); if (drawctxt || (flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) *ringcmds++ = CACHE_FLUSH_TS | (1 << 31); else *ringcmds++ = CACHE_FLUSH_TS; if (drawctxt && !(flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) { Loading @@ -723,11 +722,6 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb, *ringcmds++ = timestamp; } if (drawctxt || (flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) { *ringcmds++ = cp_packet(adreno_dev, CP_INTERRUPT, 1); *ringcmds++ = CP_INTERRUPT_RB; } if (adreno_is_a3xx(adreno_dev)) { /* Dummy set-constant to trigger context rollover */ *ringcmds++ = cp_packet(adreno_dev, CP_SET_CONSTANT, 2); Loading Loading
drivers/gpu/msm/adreno_a3xx.c +2 −1 Original line number Diff line number Diff line Loading @@ -751,6 +751,7 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit) (1 << A3XX_INT_CP_IB1_INT) | \ (1 << A3XX_INT_CP_IB2_INT) | \ (1 << A3XX_INT_CP_RB_INT) | \ (1 << A3XX_INT_CACHE_FLUSH_TS) | \ (1 << A3XX_INT_CP_REG_PROTECT_FAULT) | \ (1 << A3XX_INT_CP_AHB_ERROR_HALT) | \ (1 << A3XX_INT_UCHE_OOB_ACCESS)) Loading Loading @@ -778,7 +779,7 @@ static struct adreno_irq_funcs a3xx_irq_funcs[] = { ADRENO_IRQ_CALLBACK(NULL), /* 17 - CP_RB_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 18 - CP_VS_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 19 - CP_PS_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 20 - CP_CACHE_FLUSH_TS */ ADRENO_IRQ_CALLBACK(adreno_cp_callback), /* 20 - CP_CACHE_FLUSH_TS */ /* 21 - CP_AHB_ERROR_FAULT */ ADRENO_IRQ_CALLBACK(a3xx_err_callback), ADRENO_IRQ_CALLBACK(NULL), /* 22 - Unused */ Loading
drivers/gpu/msm/adreno_a4xx.c +2 −1 Original line number Diff line number Diff line Loading @@ -1719,6 +1719,7 @@ static struct adreno_coresight a4xx_coresight = { (1 << A4XX_INT_CP_IB1_INT) | \ (1 << A4XX_INT_CP_IB2_INT) | \ (1 << A4XX_INT_CP_RB_INT) | \ (1 << A4XX_INT_CACHE_FLUSH_TS) | \ (1 << A4XX_INT_CP_REG_PROTECT_FAULT) | \ (1 << A4XX_INT_CP_AHB_ERROR_HALT) | \ (1 << A4XX_INT_RBBM_ATB_BUS_OVERFLOW) | \ Loading Loading @@ -1755,7 +1756,7 @@ static struct adreno_irq_funcs a4xx_irq_funcs[] = { ADRENO_IRQ_CALLBACK(NULL), /* 17 - CP_RB_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 18 - CP_VS_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 19 - CP_PS_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 20 - CP_CACHE_FLUSH_TS */ ADRENO_IRQ_CALLBACK(adreno_cp_callback), /* 20 - CP_CACHE_FLUSH_TS */ /* 21 - CP_AHB_ERROR_FAULT */ ADRENO_IRQ_CALLBACK(a4xx_err_callback), ADRENO_IRQ_CALLBACK(a4xx_err_callback), /* 22 - RBBM_ATB_BUS_OVERFLOW */ Loading
drivers/gpu/msm/adreno_a5xx.c +2 −1 Original line number Diff line number Diff line Loading @@ -2790,6 +2790,7 @@ static void a5xx_gpmu_int_callback(struct adreno_device *adreno_dev, int bit) (1 << A5XX_INT_CP_IB1) | \ (1 << A5XX_INT_CP_IB2) | \ (1 << A5XX_INT_CP_RB) | \ (1 << A5XX_INT_CP_CACHE_FLUSH_TS) | \ (1 << A5XX_INT_RBBM_ATB_BUS_OVERFLOW) | \ (1 << A5XX_INT_UCHE_OOB_ACCESS) | \ (1 << A5XX_INT_UCHE_TRAP_INTR) | \ Loading Loading @@ -2826,7 +2827,7 @@ static struct adreno_irq_funcs a5xx_irq_funcs[] = { ADRENO_IRQ_CALLBACK(NULL), /* 17 - CP_RB_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 18 - CP_WT_DONE_TS */ ADRENO_IRQ_CALLBACK(NULL), /* 19 - UNKNOWN_1 */ ADRENO_IRQ_CALLBACK(NULL), /* 20 - CP_CACHE_FLUSH_TS */ ADRENO_IRQ_CALLBACK(adreno_cp_callback), /* 20 - CP_CACHE_FLUSH_TS */ /* 21 - UNUSED_2 */ ADRENO_IRQ_CALLBACK(NULL), ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 22 - RBBM_ATB_BUS_OVERFLOW */ Loading
drivers/gpu/msm/adreno_ringbuffer.c +4 −10 Original line number Diff line number Diff line Loading @@ -565,10 +565,6 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb, total_sizedwords += (secured_ctxt) ? 26 : 0; /* Add two dwords for the CP_INTERRUPT */ total_sizedwords += (drawctxt || (flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) ? 2 : 0; /* context rollover */ if (adreno_is_a3xx(adreno_dev)) total_sizedwords += 3; Loading Loading @@ -707,6 +703,9 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb, * set and hence the rb timestamp will be used in else statement below. */ *ringcmds++ = cp_mem_packet(adreno_dev, CP_EVENT_WRITE, 3, 1); if (drawctxt || (flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) *ringcmds++ = CACHE_FLUSH_TS | (1 << 31); else *ringcmds++ = CACHE_FLUSH_TS; if (drawctxt && !(flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) { Loading @@ -723,11 +722,6 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb, *ringcmds++ = timestamp; } if (drawctxt || (flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) { *ringcmds++ = cp_packet(adreno_dev, CP_INTERRUPT, 1); *ringcmds++ = CP_INTERRUPT_RB; } if (adreno_is_a3xx(adreno_dev)) { /* Dummy set-constant to trigger context rollover */ *ringcmds++ = cp_packet(adreno_dev, CP_SET_CONSTANT, 2); Loading