Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1a8ca750 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon: fix gpu_init on si 



- Properly set up the RBs
- Properly set up the SPI
- Properly set up gb_addr_config

This should fix rendering issues on certain cards.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 7838e05a

drivers/gpu/drm/radeon/radeon.h

+2 −3
Original line number Original line Diff line number Diff line
@@ -1374,9 +1374,9 @@ struct cayman_asic { 




struct si_asic {

struct si_asic {

	unsigned max_shader_engines;

	unsigned max_shader_engines;

	unsigned max_pipes_per_simd;

	unsigned max_tile_pipes;

	unsigned max_tile_pipes;

	unsigned max_simds_per_se;

	unsigned max_cu_per_sh;

	unsigned max_sh_per_se;

	unsigned max_backends_per_se;

	unsigned max_backends_per_se;

	unsigned max_texture_channel_caches;

	unsigned max_texture_channel_caches;

	unsigned max_gprs;

	unsigned max_gprs;
@@ -1387,7 +1387,6 @@ struct si_asic { 
	unsigned sc_hiz_tile_fifo_size;

	unsigned sc_hiz_tile_fifo_size;

	unsigned sc_earlyz_tile_fifo_size;

	unsigned sc_earlyz_tile_fifo_size;





	unsigned num_shader_engines;

	unsigned num_tile_pipes;

	unsigned num_tile_pipes;

	unsigned num_backends_per_se;

	unsigned num_backends_per_se;

	unsigned backend_disable_mask_per_asic;

	unsigned backend_disable_mask_per_asic;

drivers/gpu/drm/radeon/radeon_kms.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -273,7 +273,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
		break;

		break;

	case RADEON_INFO_MAX_PIPES:

	case RADEON_INFO_MAX_PIPES:

		if (rdev->family >= CHIP_TAHITI)

		if (rdev->family >= CHIP_TAHITI)

			value = rdev->config.si.max_pipes_per_simd;

			value = rdev->config.si.max_cu_per_sh;

		else if (rdev->family >= CHIP_CAYMAN)

		else if (rdev->family >= CHIP_CAYMAN)

			value = rdev->config.cayman.max_pipes_per_simd;

			value = rdev->config.cayman.max_pipes_per_simd;

		else if (rdev->family >= CHIP_CEDAR)

		else if (rdev->family >= CHIP_CEDAR)

drivers/gpu/drm/radeon/si.c

+162 −315
Original line number Original line Diff line number Diff line
@@ -867,200 +867,6 @@ void dce6_bandwidth_update(struct radeon_device *rdev) 
/*

/*

 * Core functions

 * Core functions

 */

 */

static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,

					   u32 num_tile_pipes,

					   u32 num_backends_per_asic,

					   u32 *backend_disable_mask_per_asic,

					   u32 num_shader_engines)

{

	u32 backend_map = 0;

	u32 enabled_backends_mask = 0;

	u32 enabled_backends_count = 0;

	u32 num_backends_per_se;

	u32 cur_pipe;

	u32 swizzle_pipe[SI_MAX_PIPES];

	u32 cur_backend = 0;

	u32 i;

	bool force_no_swizzle;



	/* force legal values */

	if (num_tile_pipes < 1)

		num_tile_pipes = 1;

	if (num_tile_pipes > rdev->config.si.max_tile_pipes)

		num_tile_pipes = rdev->config.si.max_tile_pipes;

	if (num_shader_engines < 1)

		num_shader_engines = 1;

	if (num_shader_engines > rdev->config.si.max_shader_engines)

		num_shader_engines = rdev->config.si.max_shader_engines;

	if (num_backends_per_asic < num_shader_engines)

		num_backends_per_asic = num_shader_engines;

	if (num_backends_per_asic > (rdev->config.si.max_backends_per_se * num_shader_engines))

		num_backends_per_asic = rdev->config.si.max_backends_per_se * num_shader_engines;



	/* make sure we have the same number of backends per se */

	num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);

	/* set up the number of backends per se */

	num_backends_per_se = num_backends_per_asic / num_shader_engines;

	if (num_backends_per_se > rdev->config.si.max_backends_per_se) {

		num_backends_per_se = rdev->config.si.max_backends_per_se;

		num_backends_per_asic = num_backends_per_se * num_shader_engines;

	}



	/* create enable mask and count for enabled backends */

	for (i = 0; i < SI_MAX_BACKENDS; ++i) {

		if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {

			enabled_backends_mask |= (1 << i);

			++enabled_backends_count;

		}

		if (enabled_backends_count == num_backends_per_asic)

			break;

	}



	/* force the backends mask to match the current number of backends */

	if (enabled_backends_count != num_backends_per_asic) {

		u32 this_backend_enabled;

		u32 shader_engine;

		u32 backend_per_se;



		enabled_backends_mask = 0;

		enabled_backends_count = 0;

		*backend_disable_mask_per_asic = SI_MAX_BACKENDS_MASK;

		for (i = 0; i < SI_MAX_BACKENDS; ++i) {

			/* calc the current se */

			shader_engine = i / rdev->config.si.max_backends_per_se;

			/* calc the backend per se */

			backend_per_se = i % rdev->config.si.max_backends_per_se;

			/* default to not enabled */

			this_backend_enabled = 0;

			if ((shader_engine < num_shader_engines) &&

			    (backend_per_se < num_backends_per_se))

				this_backend_enabled = 1;

			if (this_backend_enabled) {

				enabled_backends_mask |= (1 << i);

				*backend_disable_mask_per_asic &= ~(1 << i);

				++enabled_backends_count;

			}

		}

	}





	memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * SI_MAX_PIPES);

	switch (rdev->family) {

	case CHIP_TAHITI:

	case CHIP_PITCAIRN:

	case CHIP_VERDE:

		force_no_swizzle = true;

		break;

	default:

		force_no_swizzle = false;

		break;

	}

	if (force_no_swizzle) {

		bool last_backend_enabled = false;



		force_no_swizzle = false;

		for (i = 0; i < SI_MAX_BACKENDS; ++i) {

			if (((enabled_backends_mask >> i) & 1) == 1) {

				if (last_backend_enabled)

					force_no_swizzle = true;

				last_backend_enabled = true;

			} else

				last_backend_enabled = false;

		}

	}



	switch (num_tile_pipes) {

	case 1:

	case 3:

	case 5:

	case 7:

		DRM_ERROR("odd number of pipes!\n");

		break;

	case 2:

		swizzle_pipe[0] = 0;

		swizzle_pipe[1] = 1;

		break;

	case 4:

		if (force_no_swizzle) {

			swizzle_pipe[0] = 0;

			swizzle_pipe[1] = 1;

			swizzle_pipe[2] = 2;

			swizzle_pipe[3] = 3;

		} else {

			swizzle_pipe[0] = 0;

			swizzle_pipe[1] = 2;

			swizzle_pipe[2] = 1;

			swizzle_pipe[3] = 3;

		}

		break;

	case 6:

		if (force_no_swizzle) {

			swizzle_pipe[0] = 0;

			swizzle_pipe[1] = 1;

			swizzle_pipe[2] = 2;

			swizzle_pipe[3] = 3;

			swizzle_pipe[4] = 4;

			swizzle_pipe[5] = 5;

		} else {

			swizzle_pipe[0] = 0;

			swizzle_pipe[1] = 2;

			swizzle_pipe[2] = 4;

			swizzle_pipe[3] = 1;

			swizzle_pipe[4] = 3;

			swizzle_pipe[5] = 5;

		}

		break;

	case 8:

		if (force_no_swizzle) {

			swizzle_pipe[0] = 0;

			swizzle_pipe[1] = 1;

			swizzle_pipe[2] = 2;

			swizzle_pipe[3] = 3;

			swizzle_pipe[4] = 4;

			swizzle_pipe[5] = 5;

			swizzle_pipe[6] = 6;

			swizzle_pipe[7] = 7;

		} else {

			swizzle_pipe[0] = 0;

			swizzle_pipe[1] = 2;

			swizzle_pipe[2] = 4;

			swizzle_pipe[3] = 6;

			swizzle_pipe[4] = 1;

			swizzle_pipe[5] = 3;

			swizzle_pipe[6] = 5;

			swizzle_pipe[7] = 7;

		}

		break;

	}



	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {

		while (((1 << cur_backend) & enabled_backends_mask) == 0)

			cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;



		backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));



		cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;

	}



	return backend_map;

}



static u32 si_get_disable_mask_per_asic(struct radeon_device *rdev,

					u32 disable_mask_per_se,

					u32 max_disable_mask_per_se,

					u32 num_shader_engines)

{

	u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);

	u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;



	if (num_shader_engines == 1)

		return disable_mask_per_asic;

	else if (num_shader_engines == 2)

		return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);

	else

		return 0xffffffff;

}



static void si_tiling_mode_table_init(struct radeon_device *rdev)

static void si_tiling_mode_table_init(struct radeon_device *rdev)

{

{

	const u32 num_tile_mode_states = 32;

	const u32 num_tile_mode_states = 32;
@@ -1562,18 +1368,151 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
		DRM_ERROR("unknown asic: 0x%x\n", rdev->family);

		DRM_ERROR("unknown asic: 0x%x\n", rdev->family);

}

}





static void si_select_se_sh(struct radeon_device *rdev,

			    u32 se_num, u32 sh_num)

{

	u32 data = INSTANCE_BROADCAST_WRITES;



	if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))

		data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;

	else if (se_num == 0xffffffff)

		data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);

	else if (sh_num == 0xffffffff)

		data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);

	else

		data |= SH_INDEX(sh_num) | SE_INDEX(se_num);

	WREG32(GRBM_GFX_INDEX, data);

}



static u32 si_create_bitmask(u32 bit_width)

{

	u32 i, mask = 0;



	for (i = 0; i < bit_width; i++) {

		mask <<= 1;

		mask |= 1;

	}

	return mask;

}



static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)

{

	u32 data, mask;



	data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);

	if (data & 1)

		data &= INACTIVE_CUS_MASK;

	else

		data = 0;

	data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);



	data >>= INACTIVE_CUS_SHIFT;



	mask = si_create_bitmask(cu_per_sh);



	return ~data & mask;

}



static void si_setup_spi(struct radeon_device *rdev,

			 u32 se_num, u32 sh_per_se,

			 u32 cu_per_sh)

{

	int i, j, k;

	u32 data, mask, active_cu;



	for (i = 0; i < se_num; i++) {

		for (j = 0; j < sh_per_se; j++) {

			si_select_se_sh(rdev, i, j);

			data = RREG32(SPI_STATIC_THREAD_MGMT_3);

			active_cu = si_get_cu_enabled(rdev, cu_per_sh);



			mask = 1;

			for (k = 0; k < 16; k++) {

				mask <<= k;

				if (active_cu & mask) {

					data &= ~mask;

					WREG32(SPI_STATIC_THREAD_MGMT_3, data);

					break;

				}

			}

		}

	}

	si_select_se_sh(rdev, 0xffffffff, 0xffffffff);

}



static u32 si_get_rb_disabled(struct radeon_device *rdev,

			      u32 max_rb_num, u32 se_num,

			      u32 sh_per_se)

{

	u32 data, mask;



	data = RREG32(CC_RB_BACKEND_DISABLE);

	if (data & 1)

		data &= BACKEND_DISABLE_MASK;

	else

		data = 0;

	data |= RREG32(GC_USER_RB_BACKEND_DISABLE);



	data >>= BACKEND_DISABLE_SHIFT;



	mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);



	return data & mask;

}



static void si_setup_rb(struct radeon_device *rdev,

			u32 se_num, u32 sh_per_se,

			u32 max_rb_num)

{

	int i, j;

	u32 data, mask;

	u32 disabled_rbs = 0;

	u32 enabled_rbs = 0;



	for (i = 0; i < se_num; i++) {

		for (j = 0; j < sh_per_se; j++) {

			si_select_se_sh(rdev, i, j);

			data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);

			disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);

		}

	}

	si_select_se_sh(rdev, 0xffffffff, 0xffffffff);



	mask = 1;

	for (i = 0; i < max_rb_num; i++) {

		if (!(disabled_rbs & mask))

			enabled_rbs |= mask;

		mask <<= 1;

	}



	for (i = 0; i < se_num; i++) {

		si_select_se_sh(rdev, i, 0xffffffff);

		data = 0;

		for (j = 0; j < sh_per_se; j++) {

			switch (enabled_rbs & 3) {

			case 1:

				data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);

				break;

			case 2:

				data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);

				break;

			case 3:

			default:

				data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);

				break;

			}

			enabled_rbs >>= 2;

		}

		WREG32(PA_SC_RASTER_CONFIG, data);

	}

	si_select_se_sh(rdev, 0xffffffff, 0xffffffff);

}



static void si_gpu_init(struct radeon_device *rdev)

static void si_gpu_init(struct radeon_device *rdev)

{

{

	u32 cc_rb_backend_disable = 0;

	u32 cc_gc_shader_array_config;

	u32 gb_addr_config = 0;

	u32 gb_addr_config = 0;

	u32 mc_shared_chmap, mc_arb_ramcfg;

	u32 mc_shared_chmap, mc_arb_ramcfg;

	u32 gb_backend_map;

	u32 cgts_tcc_disable;

	u32 sx_debug_1;

	u32 sx_debug_1;

	u32 gc_user_shader_array_config;

	u32 gc_user_rb_backend_disable;

	u32 cgts_user_tcc_disable;

	u32 hdp_host_path_cntl;

	u32 hdp_host_path_cntl;

	u32 tmp;

	u32 tmp;

	int i, j;

	int i, j;
@@ -1581,9 +1520,9 @@ static void si_gpu_init(struct radeon_device *rdev) 
	switch (rdev->family) {

	switch (rdev->family) {

	case CHIP_TAHITI:

	case CHIP_TAHITI:

		rdev->config.si.max_shader_engines = 2;

		rdev->config.si.max_shader_engines = 2;

		rdev->config.si.max_pipes_per_simd = 4;

		rdev->config.si.max_tile_pipes = 12;

		rdev->config.si.max_tile_pipes = 12;

		rdev->config.si.max_simds_per_se = 8;

		rdev->config.si.max_cu_per_sh = 8;

		rdev->config.si.max_sh_per_se = 2;

		rdev->config.si.max_backends_per_se = 4;

		rdev->config.si.max_backends_per_se = 4;

		rdev->config.si.max_texture_channel_caches = 12;

		rdev->config.si.max_texture_channel_caches = 12;

		rdev->config.si.max_gprs = 256;

		rdev->config.si.max_gprs = 256;
@@ -1594,12 +1533,13 @@ static void si_gpu_init(struct radeon_device *rdev) 
		rdev->config.si.sc_prim_fifo_size_backend = 0x100;

		rdev->config.si.sc_prim_fifo_size_backend = 0x100;

		rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

		rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

		gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;

		break;

		break;

	case CHIP_PITCAIRN:

	case CHIP_PITCAIRN:

		rdev->config.si.max_shader_engines = 2;

		rdev->config.si.max_shader_engines = 2;

		rdev->config.si.max_pipes_per_simd = 4;

		rdev->config.si.max_tile_pipes = 8;

		rdev->config.si.max_tile_pipes = 8;

		rdev->config.si.max_simds_per_se = 5;

		rdev->config.si.max_cu_per_sh = 5;

		rdev->config.si.max_sh_per_se = 2;

		rdev->config.si.max_backends_per_se = 4;

		rdev->config.si.max_backends_per_se = 4;

		rdev->config.si.max_texture_channel_caches = 8;

		rdev->config.si.max_texture_channel_caches = 8;

		rdev->config.si.max_gprs = 256;

		rdev->config.si.max_gprs = 256;
@@ -1610,13 +1550,14 @@ static void si_gpu_init(struct radeon_device *rdev) 
		rdev->config.si.sc_prim_fifo_size_backend = 0x100;

		rdev->config.si.sc_prim_fifo_size_backend = 0x100;

		rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

		rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

		gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;

		break;

		break;

	case CHIP_VERDE:

	case CHIP_VERDE:

	default:

	default:

		rdev->config.si.max_shader_engines = 1;

		rdev->config.si.max_shader_engines = 1;

		rdev->config.si.max_pipes_per_simd = 4;

		rdev->config.si.max_tile_pipes = 4;

		rdev->config.si.max_tile_pipes = 4;

		rdev->config.si.max_simds_per_se = 2;

		rdev->config.si.max_cu_per_sh = 2;

		rdev->config.si.max_sh_per_se = 2;

		rdev->config.si.max_backends_per_se = 4;

		rdev->config.si.max_backends_per_se = 4;

		rdev->config.si.max_texture_channel_caches = 4;

		rdev->config.si.max_texture_channel_caches = 4;

		rdev->config.si.max_gprs = 256;

		rdev->config.si.max_gprs = 256;
@@ -1627,6 +1568,7 @@ static void si_gpu_init(struct radeon_device *rdev) 
		rdev->config.si.sc_prim_fifo_size_backend = 0x40;

		rdev->config.si.sc_prim_fifo_size_backend = 0x40;

		rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.si.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

		rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;

		gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;

		break;

		break;

	}

	}
@@ -1648,31 +1590,7 @@ static void si_gpu_init(struct radeon_device *rdev) 
	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);

	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);

	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);

	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);





	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);

	cc_gc_shader_array_config = RREG32(CC_GC_SHADER_ARRAY_CONFIG);

	cgts_tcc_disable = 0xffff0000;

	for (i = 0; i < rdev->config.si.max_texture_channel_caches; i++)

		cgts_tcc_disable &= ~(1 << (16 + i));

	gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);

	gc_user_shader_array_config = RREG32(GC_USER_SHADER_ARRAY_CONFIG);

	cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);



	rdev->config.si.num_shader_engines = rdev->config.si.max_shader_engines;

	rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;

	rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;

	tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;

	rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp);

	tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;

	rdev->config.si.backend_disable_mask_per_asic =

		si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK,

					     rdev->config.si.num_shader_engines);

	rdev->config.si.backend_map =

		si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,

						rdev->config.si.num_backends_per_se *

						rdev->config.si.num_shader_engines,

						&rdev->config.si.backend_disable_mask_per_asic,

						rdev->config.si.num_shader_engines);

	tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;

	rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp);

	rdev->config.si.mem_max_burst_length_bytes = 256;

	rdev->config.si.mem_max_burst_length_bytes = 256;

	tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;

	tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;

	rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;

	rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
@@ -1683,55 +1601,8 @@ static void si_gpu_init(struct radeon_device *rdev) 
	rdev->config.si.num_gpus = 1;

	rdev->config.si.num_gpus = 1;

	rdev->config.si.multi_gpu_tile_size = 64;

	rdev->config.si.multi_gpu_tile_size = 64;





	gb_addr_config = 0;

	/* fix up row size */

	switch (rdev->config.si.num_tile_pipes) {

	gb_addr_config &= ~ROW_SIZE_MASK;

	case 1:

		gb_addr_config |= NUM_PIPES(0);

		break;

	case 2:

		gb_addr_config |= NUM_PIPES(1);

		break;

	case 4:

		gb_addr_config |= NUM_PIPES(2);

		break;

	case 8:

	default:

		gb_addr_config |= NUM_PIPES(3);

		break;

	}



	tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1;

	gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);

	gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.si.num_shader_engines - 1);

	tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1;

	gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);

	switch (rdev->config.si.num_gpus) {

	case 1:

	default:

		gb_addr_config |= NUM_GPUS(0);

		break;

	case 2:

		gb_addr_config |= NUM_GPUS(1);

		break;

	case 4:

		gb_addr_config |= NUM_GPUS(2);

		break;

	}

	switch (rdev->config.si.multi_gpu_tile_size) {

	case 16:

		gb_addr_config |= MULTI_GPU_TILE_SIZE(0);

		break;

	case 32:

	default:

		gb_addr_config |= MULTI_GPU_TILE_SIZE(1);

		break;

	case 64:

		gb_addr_config |= MULTI_GPU_TILE_SIZE(2);

		break;

	case 128:

		gb_addr_config |= MULTI_GPU_TILE_SIZE(3);

		break;

	}

	switch (rdev->config.si.mem_row_size_in_kb) {

	switch (rdev->config.si.mem_row_size_in_kb) {

	case 1:

	case 1:

	default:

	default:
@@ -1745,26 +1616,6 @@ static void si_gpu_init(struct radeon_device *rdev) 
		break;

		break;

	}

	}





	tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;

	rdev->config.si.num_tile_pipes = (1 << tmp);

	tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;

	rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256;

	tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;

	rdev->config.si.num_shader_engines = tmp + 1;

	tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;

	rdev->config.si.num_gpus = tmp + 1;

	tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;

	rdev->config.si.multi_gpu_tile_size = 1 << tmp;

	tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;

	rdev->config.si.mem_row_size_in_kb = 1 << tmp;



	gb_backend_map =

		si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,

						rdev->config.si.num_backends_per_se *

						rdev->config.si.num_shader_engines,

						&rdev->config.si.backend_disable_mask_per_asic,

						rdev->config.si.num_shader_engines);



	/* setup tiling info dword.  gb_addr_config is not adequate since it does

	/* setup tiling info dword.  gb_addr_config is not adequate since it does

	 * not have bank info, so create a custom tiling dword.

	 * not have bank info, so create a custom tiling dword.

	 * bits 3:0   num_pipes

	 * bits 3:0   num_pipes
@@ -1789,33 +1640,29 @@ static void si_gpu_init(struct radeon_device *rdev) 
		rdev->config.si.tile_config |= (3 << 0);

		rdev->config.si.tile_config |= (3 << 0);

		break;

		break;

	}

	}

	rdev->config.si.tile_config |=

	if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)

		((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;

		rdev->config.si.tile_config |= 1 << 4;

	else

		rdev->config.si.tile_config |= 0 << 4;

	rdev->config.si.tile_config |=

	rdev->config.si.tile_config |=

		((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;

		((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;

	rdev->config.si.tile_config |=

	rdev->config.si.tile_config |=

		((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;

		((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;





	rdev->config.si.backend_map = gb_backend_map;

	WREG32(GB_ADDR_CONFIG, gb_addr_config);

	WREG32(GB_ADDR_CONFIG, gb_addr_config);

	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);





	/* primary versions */

	si_tiling_mode_table_init(rdev);

	WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);

	WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);

	WREG32(CC_GC_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);



	WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);





	/* user versions */

	si_setup_rb(rdev, rdev->config.si.max_shader_engines,

	WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);

		    rdev->config.si.max_sh_per_se,

	WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);

		    rdev->config.si.max_backends_per_se);

	WREG32(GC_USER_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);





	WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);

	si_setup_spi(rdev, rdev->config.si.max_shader_engines,

		     rdev->config.si.max_sh_per_se,

		     rdev->config.si.max_cu_per_sh);





	si_tiling_mode_table_init(rdev);





	/* set HW defaults for 3D engine */

	/* set HW defaults for 3D engine */

	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |

	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |

drivers/gpu/drm/radeon/sid.h

+19 −0
Original line number Original line Diff line number Diff line
@@ -24,6 +24,11 @@ 
#ifndef SI_H

#ifndef SI_H

#define SI_H

#define SI_H





#define TAHITI_RB_BITMAP_WIDTH_PER_SH  2



#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003

#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002



#define	CG_MULT_THERMAL_STATUS					0x714

#define	CG_MULT_THERMAL_STATUS					0x714

#define		ASIC_MAX_TEMP(x)				((x) << 0)

#define		ASIC_MAX_TEMP(x)				((x) << 0)

#define		ASIC_MAX_TEMP_MASK				0x000001ff

#define		ASIC_MAX_TEMP_MASK				0x000001ff
@@ -408,6 +413,12 @@ 
#define		SOFT_RESET_IA					(1 << 15)

#define		SOFT_RESET_IA					(1 << 15)





#define GRBM_GFX_INDEX          			0x802C

#define GRBM_GFX_INDEX          			0x802C

#define		INSTANCE_INDEX(x)			((x) << 0)

#define		SH_INDEX(x)     			((x) << 8)

#define		SE_INDEX(x)     			((x) << 16)

#define		SH_BROADCAST_WRITES      		(1 << 29)

#define		INSTANCE_BROADCAST_WRITES      		(1 << 30)

#define		SE_BROADCAST_WRITES      		(1 << 31)





#define GRBM_INT_CNTL                                   0x8060

#define GRBM_INT_CNTL                                   0x8060

#       define RDERR_INT_ENABLE                         (1 << 0)

#       define RDERR_INT_ENABLE                         (1 << 0)
@@ -480,6 +491,8 @@ 
#define	VGT_TF_MEMORY_BASE				0x89B8

#define	VGT_TF_MEMORY_BASE				0x89B8





#define CC_GC_SHADER_ARRAY_CONFIG			0x89bc

#define CC_GC_SHADER_ARRAY_CONFIG			0x89bc

#define		INACTIVE_CUS_MASK			0xFFFF0000

#define		INACTIVE_CUS_SHIFT			16

#define GC_USER_SHADER_ARRAY_CONFIG			0x89c0

#define GC_USER_SHADER_ARRAY_CONFIG			0x89c0





#define	PA_CL_ENHANCE					0x8A14

#define	PA_CL_ENHANCE					0x8A14
@@ -688,6 +701,12 @@ 
#define RLC_MC_CNTL                                       0xC344

#define RLC_MC_CNTL                                       0xC344

#define RLC_UCODE_CNTL                                    0xC348

#define RLC_UCODE_CNTL                                    0xC348





#define PA_SC_RASTER_CONFIG                             0x28350

#       define RASTER_CONFIG_RB_MAP_0                   0

#       define RASTER_CONFIG_RB_MAP_1                   1

#       define RASTER_CONFIG_RB_MAP_2                   2

#       define RASTER_CONFIG_RB_MAP_3                   3



#define VGT_EVENT_INITIATOR                             0x28a90

#define VGT_EVENT_INITIATOR                             0x28a90

#       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)

#       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)

#       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)

#       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)