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Commit 1a55eff3 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Gerrit - the friendly Code Review server
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clk: msm: clock-8996: Remove HLOS support for aggre0_noc_at_clk 



Due to a hardware workaround, the gcc_aggre0_noc_at_clk clock
will be enabled by the XBL at boot and be left on. HLOS no
longer needs to control this clock which will now be turned
on automatically when the aggre0_noc GDSC is enabled.
Remove the clock driver support for this clock. In addition,
remove the QDSS Aggre0Noc bus node which was required for the
data path from PCIe masters.

Change-Id: I6ad90c492814449fbf3a57e50cab67956c177507
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: default avatarGirish Mahadevan <girishm@codeaurora.org>
parent ef0d0e07

arch/arm/boot/dts/qcom/msm8996-bus.dtsi

+3 −17
Original line number Diff line number Diff line
@@ -239,7 +239,7 @@ 
			qcom,ap-owned;

			qcom,qport = <0>;

			qcom,qos-mode = "fixed";

			qcom,connections = <&slv_a0noc_qdss>;

			qcom,connections = <&slv_a0noc_snoc>;

			qcom,prio1 = <1>;

			qcom,prio0 = <1>;

			qcom,bus-dev = <&fab_a0noc>;
@@ -254,7 +254,7 @@ 
			qcom,ap-owned;

			qcom,qport = <1>;

			qcom,qos-mode = "fixed";

			qcom,connections = <&slv_a0noc_qdss>;

			qcom,connections = <&slv_a0noc_snoc>;

			qcom,prio1 = <1>;

			qcom,prio0 = <1>;

			qcom,bus-dev = <&fab_a0noc>;
@@ -269,7 +269,7 @@ 
			qcom,ap-owned;

			qcom,qport = <2>;

			qcom,qos-mode = "fixed";

			qcom,connections = <&slv_a0noc_qdss>;

			qcom,connections = <&slv_a0noc_snoc>;

			qcom,prio1 = <1>;

			qcom,prio0 = <1>;

			qcom,bus-dev = <&fab_a0noc>;
@@ -825,20 +825,6 @@ 


		/*Slaves*/



		slv_a0noc_qdss: slv-a0noc-qdss {

			cell-id = <MSM_BUS_A0NOC_QDSS_INT>;

			label = "slv-a0noc-qdss";

			qcom,buswidth = <8>;

			qcom,agg-ports = <1>;

			qcom,ap-owned;

			qcom,bus-dev = <&fab_a0noc>;

			qcom,connections = <&slv_a0noc_snoc>;

			qcom,slv-rpm-id = <ICBID_SLAVE_A0NOC_SNOC>;

			qcom,enable-only-clk;

			clock-names = "node_clk";

			clocks = <&clock_gcc clk_gcc_aggre0_noc_at_clk>;

		};



		slv_a0noc_snoc: slv-a0noc-snoc {

			cell-id = <MSM_BUS_A0NOC_SNOC_SLV>;

			label = "slv-a0noc-snoc";

drivers/clk/msm/clock-gcc-8996.c

+0 −14
Original line number Diff line number Diff line
@@ -1639,18 +1639,6 @@ static struct branch_clk gcc_smmu_aggre0_axi_clk = { 
	},

};



static struct branch_clk gcc_aggre0_noc_at_clk = {

	.cbcr_reg = GCC_AGGRE0_NOC_AT_CBCR,

	.has_sibling = 1,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_aggre0_noc_at_clk",

		.always_on = true,

		.ops = &clk_ops_branch,

		CLK_INIT(gcc_aggre0_noc_at_clk.c),

	},

};



static struct gate_clk gcc_aggre0_noc_qosgen_extref_clk = {

	.en_reg = GCC_AGGRE0_NOC_QOSGEN_EXTREF_CTL,

	.en_mask = BIT(0),
@@ -3293,7 +3281,6 @@ static struct mux_clk gcc_debug_mux = { 
		{ &gcc_ufs_tx_symbol_clk_core_clk.c, 0x0109 },

		{ &gcc_aggre0_snoc_axi_clk.c, 0x0116 },

		{ &gcc_aggre0_cnoc_ahb_clk.c, 0x0117 },

		{ &gcc_aggre0_noc_at_clk.c, 0x0118 },

		{ &gcc_smmu_aggre0_axi_clk.c, 0x0119 },

		{ &gcc_smmu_aggre0_ahb_clk.c, 0x011a },

		{ &gcc_aggre0_noc_qosgen_extref_clk.c, 0x011b },
@@ -3469,7 +3456,6 @@ static struct clk_lookup msm_clocks_gcc_8996[] = { 
	CLK_LIST(gcc_aggre0_snoc_axi_clk),

	CLK_LIST(gcc_smmu_aggre0_ahb_clk),

	CLK_LIST(gcc_smmu_aggre0_axi_clk),

	CLK_LIST(gcc_aggre0_noc_at_clk),

	CLK_LIST(gcc_aggre0_noc_qosgen_extref_clk),

	CLK_LIST(gcc_aggre2_usb3_axi_clk),

	CLK_LIST(gcc_aggre2_ufs_axi_clk),

include/dt-bindings/clock/msm-clocks-8996.h

+0 −1
Original line number Diff line number Diff line
@@ -253,7 +253,6 @@ 
#define clk_gcc_usb_phy_cfg_ahb2phy_clk	0xd1231a0e

#define clk_gcc_aggre0_cnoc_ahb_clk	0x53a35559

#define clk_gcc_aggre0_snoc_axi_clk	0x3c446400

#define clk_gcc_aggre0_noc_at_clk	0xf753290f

#define clk_gcc_aggre0_noc_qosgen_extref_clk	0x8c4356ba

#define clk_hlos1_vote_lpass_core_smmu_clk	0x3aaa1743

#define clk_hlos1_vote_lpass_adsp_smmu_clk	0xc76f702f

include/dt-bindings/clock/msm-clocks-hwio-8996.h

+0 −1
Original line number Diff line number Diff line
@@ -460,7 +460,6 @@ 
#define GCC_PRNG_BCR						(0x34000)

#define GCC_AGGRE0_SNOC_AXI_CBCR				(0x81008)

#define GCC_AGGRE0_CNOC_AHB_CBCR				(0x8100C)

#define GCC_AGGRE0_NOC_AT_CBCR					(0x81010)

#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CTL			(0x8101C)

#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR			(0x7D010)

#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR			(0x7D014)