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Commit 1a467fcb authored by Carter Cooper's avatar Carter Cooper
Browse files

msm: kgsl: Cleanup CP queue threshold programming logic 



Simplify the logic for writing the CP queue threshold register
since readability is nine tenths of the law. More specifically,
don't do a billion (or 8) checks for the old targets.

Change-Id: Ia47088261602cbe455e00d5f8b1e74bbb967d3a1
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent 031e28bb

drivers/gpu/msm/adreno_ringbuffer.c

+9 −8
Original line number Diff line number Diff line
@@ -303,14 +303,15 @@ static void _ringbuffer_setup_common(struct adreno_ringbuffer *rb) 
			  ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc.gpuaddr);



	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */

	if (adreno_is_a305(adreno_dev) || adreno_is_a305c(adreno_dev) ||

		adreno_is_a306(adreno_dev) || adreno_is_a306a(adreno_dev) ||

		adreno_is_a320(adreno_dev) ||

		adreno_is_a304(adreno_dev))

		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x000E0602);

	else if (adreno_is_a330(adreno_dev) || adreno_is_a305b(adreno_dev) ||

			adreno_is_a310(adreno_dev))

		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x003E2008);

	if (adreno_is_a3xx(adreno_dev)) {

		unsigned int val = 0x000E0602;



		if (adreno_is_a305b(adreno_dev) ||

				adreno_is_a310(adreno_dev) ||

				adreno_is_a330(adreno_dev))

			val = 0x003E2008;

		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, val);

	}

}



/**