Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 19c55da1 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/crt: Flush register prior to waiting for vblank. 



If we don't flush the write then we can not be sure that the border
colour will have taken effect by the time we try to read it back.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 82d7c9e7

drivers/gpu/drm/i915/intel_crt.c

+1 −0
Original line number Diff line number Diff line
@@ -327,6 +327,7 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder 
	if (IS_I9XX(dev)) {

		uint32_t pipeconf = I915_READ(pipeconf_reg);

		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);

		POSTING_READ(pipeconf_reg);

		/* Wait for next Vblank to substitue

		 * border color for Color info */

		intel_wait_for_vblank(dev, pipe);