drm/nve0/gr: initial fuc implementation, based on fermi's code

/* fuc microcode for nve0 PGRAPH/GPC

 *

 * Copyright 2011 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */

/* To build:

 *    m4 nve0_grgpc.fuc | envyas -a -w -m fuc -V nva3 -o nve0_grgpc.fuc.h

 */

/* TODO

 * - bracket certain functions with scratch writes, useful for debugging

 * - watchdog timer around ctx operations

 */

.section #nve0_grgpc_data

include(`nve0.fuc')

gpc_id:			.b32 0

gpc_mmio_list_head:	.b32 0

gpc_mmio_list_tail:	.b32 0

tpc_count:		.b32 0

tpc_mask:		.b32 0

tpc_mmio_list_head:	.b32 0

tpc_mmio_list_tail:	.b32 0

cmd_queue:		queue_init

// chipset descriptions

chipsets:

.b8  0xe4 0 0 0

.b16 #nve4_gpc_mmio_head

.b16 #nve4_gpc_mmio_tail

.b16 #nve4_tpc_mmio_head

.b16 #nve4_tpc_mmio_tail

.b8  0xe7 0 0 0

.b16 #nve4_gpc_mmio_head

.b16 #nve4_gpc_mmio_tail

.b16 #nve4_tpc_mmio_head

.b16 #nve4_tpc_mmio_tail

.b8  0 0 0 0

// GPC mmio lists

nve4_gpc_mmio_head:

mmctx_data(0x000380, 1)

mmctx_data(0x000400, 2)

mmctx_data(0x00040c, 3)

mmctx_data(0x000450, 9)

mmctx_data(0x000600, 1)

mmctx_data(0x000684, 1)

mmctx_data(0x000700, 5)

mmctx_data(0x000800, 1)

mmctx_data(0x000808, 3)

mmctx_data(0x000828, 1)

mmctx_data(0x000830, 1)

mmctx_data(0x0008d8, 1)

mmctx_data(0x0008e0, 1)

mmctx_data(0x0008e8, 6)

mmctx_data(0x00091c, 1)

mmctx_data(0x000924, 3)

mmctx_data(0x000b00, 1)

mmctx_data(0x000b08, 6)

mmctx_data(0x000bb8, 1)

mmctx_data(0x000c08, 1)

mmctx_data(0x000c10, 8)

mmctx_data(0x000c40, 1)

mmctx_data(0x000c6c, 1)

mmctx_data(0x000c80, 1)

mmctx_data(0x000c8c, 1)

mmctx_data(0x001000, 3)

mmctx_data(0x001014, 1)

mmctx_data(0x003024, 1)

mmctx_data(0x0030c0, 2)

mmctx_data(0x0030e4, 1)

mmctx_data(0x003100, 6)

mmctx_data(0x0031d0, 1)

mmctx_data(0x0031e0, 2)

nve4_gpc_mmio_tail:

// TPC mmio lists

nve4_tpc_mmio_head:

mmctx_data(0x000048, 1)

mmctx_data(0x000064, 1)

mmctx_data(0x000088, 1)

mmctx_data(0x000200, 6)

mmctx_data(0x00021c, 2)

mmctx_data(0x000230, 1)

mmctx_data(0x0002c4, 1)

mmctx_data(0x000400, 3)

mmctx_data(0x000420, 3)

mmctx_data(0x0004e8, 1)

mmctx_data(0x0004f4, 1)

mmctx_data(0x000604, 4)

mmctx_data(0x000644, 22)

mmctx_data(0x0006ac, 2)

mmctx_data(0x0006c8, 1)

mmctx_data(0x000730, 8)

mmctx_data(0x000758, 1)

mmctx_data(0x000778, 1)

nve4_tpc_mmio_tail:

.section #nve0_grgpc_code

bra #init

define(`include_code')

include(`nve0.fuc')

// reports an exception to the host

//

// In: $r15 error code (see nve0.fuc)

//

error:

	push $r14

	mov $r14 -0x67ec 	// 0x9814

	sethi $r14 0x400000

	call #nv_wr32		// HUB_CTXCTL_CC_SCRATCH[5] = error code

	add b32 $r14 0x41c

	mov $r15 1

	call #nv_wr32		// HUB_CTXCTL_INTR_UP_SET

	pop $r14

	ret

// GPC fuc initialisation, executed by triggering ucode start, will

// fall through to main loop after completion.

//

// Input:

//   CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)

//   CC_SCRATCH[1]: context base

//

// Output:

//   CC_SCRATCH[0]:

//	     31:31: set to signal completion

//   CC_SCRATCH[1]:

//	      31:0: GPC context size

//

init:

	clear b32 $r0

	mov $sp $r0

	// enable fifo access

	mov $r1 0x1200

	mov $r2 2

	iowr I[$r1 + 0x000] $r2		// FIFO_ENABLE

	// setup i0 handler, and route all interrupts to it

	mov $r1 #ih

	mov $iv0 $r1

	mov $r1 0x400

	iowr I[$r1 + 0x300] $r0		// INTR_DISPATCH

	// enable fifo interrupt

	mov $r2 4

	iowr I[$r1 + 0x000] $r2		// INTR_EN_SET

	// enable interrupts

	bset $flags ie0

	// figure out which GPC we are, and how many TPCs we have

	mov $r1 0x608

	shl b32 $r1 6

	iord $r2 I[$r1 + 0x000]		// UNITS

	mov $r3 1

	and $r2 0x1f

	shl b32 $r3 $r2

	sub b32 $r3 1

	st b32 D[$r0 + #tpc_count] $r2

	st b32 D[$r0 + #tpc_mask] $r3

	add b32 $r1 0x400

	iord $r2 I[$r1 + 0x000]		// MYINDEX

	st b32 D[$r0 + #gpc_id] $r2

	// find context data for this chipset

	mov $r2 0x800

	shl b32 $r2 6

	iord $r2 I[$r2 + 0x000]		// CC_SCRATCH[0]

	mov $r1 #chipsets - 12

	init_find_chipset:

		add b32 $r1 12

		ld b32 $r3 D[$r1 + 0x00]

		cmpu b32 $r3 $r2

		bra e #init_context

		cmpu b32 $r3 0

		bra ne #init_find_chipset

		// unknown chipset

		ret

	// initialise context base, and size tracking

	init_context:

	mov $r2 0x800

	shl b32 $r2 6

	iord $r2 I[$r2 + 0x100]	// CC_SCRATCH[1], initial base

	clear b32 $r3		// track GPC context size here

	// set mmctx base addresses now so we don't have to do it later,

	// they don't currently ever change

	mov $r4 0x700

	shl b32 $r4 6

	shr b32 $r5 $r2 8

	iowr I[$r4 + 0x000] $r5		// MMCTX_SAVE_SWBASE

	iowr I[$r4 + 0x100] $r5		// MMCTX_LOAD_SWBASE

	// calculate GPC mmio context size, store the chipset-specific

	// mmio list pointers somewhere we can get at them later without

	// re-parsing the chipset list

	clear b32 $r14

	clear b32 $r15

	ld b16 $r14 D[$r1 + 4]

	ld b16 $r15 D[$r1 + 6]

	st b16 D[$r0 + #gpc_mmio_list_head] $r14

	st b16 D[$r0 + #gpc_mmio_list_tail] $r15

	call #mmctx_size

	add b32 $r2 $r15

	add b32 $r3 $r15

	// calculate per-TPC mmio context size, store the list pointers

	ld b16 $r14 D[$r1 + 8]

	ld b16 $r15 D[$r1 + 10]

	st b16 D[$r0 + #tpc_mmio_list_head] $r14

	st b16 D[$r0 + #tpc_mmio_list_tail] $r15

	call #mmctx_size

	ld b32 $r14 D[$r0 + #tpc_count]

	mulu $r14 $r15

	add b32 $r2 $r14

	add b32 $r3 $r14

	// round up base/size to 256 byte boundary (for strand SWBASE)

	add b32 $r4 0x1300

	shr b32 $r3 2

	iowr I[$r4 + 0x000] $r3		// MMCTX_LOAD_COUNT, wtf for?!?

	shr b32 $r2 8

	shr b32 $r3 6

	add b32 $r2 1

	add b32 $r3 1

	shl b32 $r2 8

	shl b32 $r3 8

	// calculate size of strand context data

	mov b32 $r15 $r2

	call #strand_ctx_init

	add b32 $r3 $r15

	// save context size, and tell HUB we're done

	mov $r1 0x800

	shl b32 $r1 6

	iowr I[$r1 + 0x100] $r3		// CC_SCRATCH[1]  = context size

	add b32 $r1 0x800

	clear b32 $r2

	bset $r2 31

	iowr I[$r1 + 0x000] $r2		// CC_SCRATCH[0] |= 0x80000000

// Main program loop, very simple, sleeps until woken up by the interrupt

// handler, pulls a command from the queue and executes its handler

//

main:

	bset $flags $p0

	sleep $p0

	mov $r13 #cmd_queue

	call #queue_get

	bra $p1 #main

	// 0x0000-0x0003 are all context transfers

	cmpu b32 $r14 0x04

	bra nc #main_not_ctx_xfer

		// fetch $flags and mask off $p1/$p2

		mov $r1 $flags

		mov $r2 0x0006

		not b32 $r2

		and $r1 $r2

		// set $p1/$p2 according to transfer type

		shl b32 $r14 1

		or $r1 $r14

		mov $flags $r1

		// transfer context data

		call #ctx_xfer

		bra #main

	main_not_ctx_xfer:

	shl b32 $r15 $r14 16

	or $r15 E_BAD_COMMAND

	call #error

	bra #main

// interrupt handler

ih:

	push $r8

	mov $r8 $flags

	push $r8

	push $r9

	push $r10

	push $r11

	push $r13

	push $r14

	push $r15

	// incoming fifo command?

	iord $r10 I[$r0 + 0x200]	// INTR

	and $r11 $r10 0x00000004

	bra e #ih_no_fifo

		// queue incoming fifo command for later processing

		mov $r11 0x1900

		mov $r13 #cmd_queue

		iord $r14 I[$r11 + 0x100]	// FIFO_CMD

		iord $r15 I[$r11 + 0x000]	// FIFO_DATA

		call #queue_put

		add b32 $r11 0x400

		mov $r14 1

		iowr I[$r11 + 0x000] $r14	// FIFO_ACK

	// ack, and wake up main()

	ih_no_fifo:

	iowr I[$r0 + 0x100] $r10	// INTR_ACK

	pop $r15

	pop $r14

	pop $r13

	pop $r11

	pop $r10

	pop $r9

	pop $r8

	mov $flags $r8

	pop $r8

	bclr $flags $p0

	iret

// Set this GPC's bit in HUB_BAR, used to signal completion of various

// activities to the HUB fuc

//

hub_barrier_done:

	mov $r15 1

	ld b32 $r14 D[$r0 + #gpc_id]

	shl b32 $r15 $r14

	mov $r14 -0x6be8 	// 0x409418 - HUB_BAR_SET

	sethi $r14 0x400000

	call #nv_wr32

	ret

// Disables various things, waits a bit, and re-enables them..

//

// Not sure how exactly this helps, perhaps "ENABLE" is not such a

// good description for the bits we turn off?  Anyways, without this,

// funny things happen.

//

ctx_redswitch:

	mov $r14 0x614

	shl b32 $r14 6

	mov $r15 0x020

	iowr I[$r14] $r15	// GPC_RED_SWITCH = POWER

	mov $r15 8

	ctx_redswitch_delay:

		sub b32 $r15 1

		bra ne #ctx_redswitch_delay

	mov $r15 0xa20

	iowr I[$r14] $r15	// GPC_RED_SWITCH = UNK11, ENABLE, POWER

	ret

// Transfer GPC context data between GPU and storage area

//

// In: $r15 context base address

//     $p1 clear on save, set on load

//     $p2 set if opposite direction done/will be done, so:

//		on save it means: "a load will follow this save"

//		on load it means: "a save preceeded this load"

//

ctx_xfer:

	// set context base address

	mov $r1 0xa04

	shl b32 $r1 6

	iowr I[$r1 + 0x000] $r15// MEM_BASE

	bra not $p1 #ctx_xfer_not_load

		call #ctx_redswitch

	ctx_xfer_not_load:

	// strands

	mov $r1 0x4afc

	sethi $r1 0x20000

	mov $r2 0xc

	iowr I[$r1] $r2		// STRAND_CMD(0x3f) = 0x0c

	call #strand_wait

	mov $r2 0x47fc

	sethi $r2 0x20000

	iowr I[$r2] $r0		// STRAND_FIRST_GENE(0x3f) = 0x00

	xbit $r2 $flags $p1

	add b32 $r2 3

	iowr I[$r1] $r2		// STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)

	// mmio context

	xbit $r10 $flags $p1	// direction

	or $r10 2		// first

	mov $r11 0x0000

	sethi $r11 0x500000

	ld b32 $r12 D[$r0 + #gpc_id]

	shl b32 $r12 15

	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn

	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]

	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]

	mov $r14 0		// not multi

	call #mmctx_xfer

	// per-TPC mmio context

	xbit $r10 $flags $p1	// direction

	or $r10 4		// last

	mov $r11 0x4000

	sethi $r11 0x500000	// base = NV_PGRAPH_GPC0_TPC0

	ld b32 $r12 D[$r0 + #gpc_id]

	shl b32 $r12 15

	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_TPC0

	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]

	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]

	ld b32 $r15 D[$r0 + #tpc_mask]

	mov $r14 0x800		// stride = 0x800

	call #mmctx_xfer

	// wait for strands to finish

	call #strand_wait

	// if load, or a save without a load following, do some

	// unknown stuff that's done after finishing a block of

	// strand commands

	bra $p1 #ctx_xfer_post

	bra not $p2 #ctx_xfer_done

	ctx_xfer_post:

		mov $r1 0x4afc

		sethi $r1 0x20000

		mov $r2 0xd

		iowr I[$r1] $r2		// STRAND_CMD(0x3f) = 0x0d

		call #strand_wait

	// mark completion in HUB's barrier

	ctx_xfer_done:

	call #hub_barrier_done

	ret

.align 256

uint32_t nve0_grgpc_data[] = {

/* 0x0000: gpc_id */

	0x00000000,

/* 0x0004: gpc_mmio_list_head */

	0x00000000,

/* 0x0008: gpc_mmio_list_tail */

	0x00000000,

/* 0x000c: tpc_count */

	0x00000000,

/* 0x0010: tpc_mask */

	0x00000000,

/* 0x0014: tpc_mmio_list_head */

	0x00000000,

/* 0x0018: tpc_mmio_list_tail */

	0x00000000,

/* 0x001c: cmd_queue */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

/* 0x0064: chipsets */

	0x000000e4,

	0x01040080,

	0x014c0104,

	0x000000e7,

	0x01040080,

	0x014c0104,

	0x00000000,

/* 0x0080: nve4_gpc_mmio_head */

	0x00000380,

	0x04000400,

	0x0800040c,

	0x20000450,

	0x00000600,

	0x00000684,

	0x10000700,

	0x00000800,

	0x08000808,

	0x00000828,

	0x00000830,

	0x000008d8,

	0x000008e0,

	0x140008e8,

	0x0000091c,

	0x08000924,

	0x00000b00,

	0x14000b08,

	0x00000bb8,

	0x00000c08,

	0x1c000c10,

	0x00000c40,

	0x00000c6c,

	0x00000c80,

	0x00000c8c,

	0x08001000,

	0x00001014,

	0x00003024,

	0x040030c0,

	0x000030e4,

	0x14003100,

	0x000031d0,

	0x040031e0,

/* 0x0104: nve4_gpc_mmio_tail */

/* 0x0104: nve4_tpc_mmio_head */

	0x00000048,

	0x00000064,

	0x00000088,

	0x14000200,

	0x0400021c,

	0x00000230,

	0x000002c4,

	0x08000400,

	0x08000420,

	0x000004e8,

	0x000004f4,

	0x0c000604,

	0x54000644,

	0x040006ac,

	0x000006c8,

	0x1c000730,

	0x00000758,

	0x00000778,

};

uint32_t nve0_grgpc_code[] = {

	0x03060ef5,

/* 0x0004: queue_put */

	0x9800d898,

	0x86f001d9,

	0x0489b808,

	0xf00c1bf4,

	0x21f502f7,

	0x00f802ec,

/* 0x001c: queue_put_next */

	0xb60798c4,

	0x8dbb0384,

	0x0880b600,

	0x80008e80,

	0x90b6018f,

	0x0f94f001,

	0xf801d980,

/* 0x0039: queue_get */

	0x0131f400,

	0x9800d898,

	0x89b801d9,

	0x210bf404,

	0xb60789c4,

	0x9dbb0394,

	0x0890b600,

	0x98009e98,

	0x80b6019f,

	0x0f84f001,

	0xf400d880,

/* 0x0066: queue_get_done */

	0x00f80132,

/* 0x0068: nv_rd32 */

	0x0728b7f1,

	0xb906b4b6,

	0xc9f002ec,

	0x00bcd01f,

/* 0x0078: nv_rd32_wait */

	0xc800bccf,

	0x1bf41fcc,

	0x06a7f0fa,

	0x010321f5,

	0xf840bfcf,

/* 0x008d: nv_wr32 */

	0x28b7f100,

	0x06b4b607,

	0xb980bfd0,

	0xc9f002ec,

	0x1ec9f01f,

/* 0x00a3: nv_wr32_wait */

	0xcf00bcd0,

	0xccc800bc,

	0xfa1bf41f,

/* 0x00ae: watchdog_reset */

	0x87f100f8,

	0x84b60430,

	0x1ff9f006,

	0xf8008fd0,

/* 0x00bd: watchdog_clear */

	0x3087f100,

	0x0684b604,

	0xf80080d0,

/* 0x00c9: wait_donez */

	0x3c87f100,

	0x0684b608,

	0x99f094bd,

	0x0089d000,

	0x081887f1,

	0xd00684b6,

/* 0x00e2: wait_done_wait_donez */

	0x87f1008a,

	0x84b60400,

	0x0088cf06,

	0xf4888aff,

	0x87f1f31b,

	0x84b6085c,

	0xf094bd06,

	0x89d00099,

/* 0x0103: wait_doneo */

	0xf100f800,

	0xb6083c87,

	0x94bd0684,

	0xd00099f0,

	0x87f10089,

	0x84b60818,

	0x008ad006,

/* 0x011c: wait_done_wait_doneo */

	0x040087f1,

	0xcf0684b6,

	0x8aff0088,

	0xf30bf488,

	0x085c87f1,

	0xbd0684b6,

	0x0099f094,

	0xf80089d0,

/* 0x013d: mmctx_size */

/* 0x013f: nv_mmctx_size_loop */

	0x9894bd00,

	0x85b600e8,

	0x0180b61a,

	0xbb0284b6,

	0xe0b60098,

	0x04efb804,

	0xb9eb1bf4,

	0x00f8029f,

/* 0x015c: mmctx_xfer */

	0x083c87f1,

	0xbd0684b6,

	0x0199f094,

	0xf10089d0,

	0xb6071087,

	0x94bd0684,

	0xf405bbfd,

	0x8bd0090b,

	0x0099f000,

/* 0x0180: mmctx_base_disabled */

	0xf405eefd,

	0x8ed00c0b,

	0xc08fd080,

/* 0x018f: mmctx_multi_disabled */

	0xb70199f0,

	0xc8010080,

	0xb4b600ab,

	0x0cb9f010,

	0xb601aec8,

	0xbefd11e4,

	0x008bd005,

/* 0x01a8: mmctx_exec_loop */

/* 0x01a8: mmctx_wait_free */

	0xf0008ecf,

	0x0bf41fe4,

	0x00ce98fa,

	0xd005e9fd,

	0xc0b6c08e,

	0x04cdb804,

	0xc8e81bf4,

	0x1bf402ab,

/* 0x01c9: mmctx_fini_wait */

	0x008bcf18,

	0xb01fb4f0,

	0x1bf410b4,

	0x02a7f0f7,

	0xf4c921f4,

/* 0x01de: mmctx_stop */

	0xabc81b0e,

	0x10b4b600,

	0xf00cb9f0,

	0x8bd012b9,

/* 0x01ed: mmctx_stop_wait */

	0x008bcf00,

	0xf412bbc8,

/* 0x01f6: mmctx_done */

	0x87f1fa1b,

	0x84b6085c,

	0xf094bd06,

	0x89d00199,

/* 0x0207: strand_wait */

	0xf900f800,

	0x02a7f0a0,

	0xfcc921f4,

/* 0x0213: strand_pre */

	0xf100f8a0,

	0xf04afc87,

	0x97f00283,

	0x0089d00c,

	0x020721f5,

/* 0x0226: strand_post */

	0x87f100f8,

	0x83f04afc,

	0x0d97f002,

	0xf50089d0,

	0xf8020721,

/* 0x0239: strand_set */

	0xfca7f100,

	0x02a3f04f,

	0x0500aba2,

	0xd00fc7f0,

	0xc7f000ac,

	0x00bcd00b,

	0x020721f5,

	0xf000aed0,

	0xbcd00ac7,

	0x0721f500,

/* 0x0263: strand_ctx_init */

	0xf100f802,

	0xb6083c87,

	0x94bd0684,

	0xd00399f0,

	0x21f50089,

	0xe7f00213,

	0x3921f503,

	0xfca7f102,

	0x02a3f046,

	0x0400aba0,

	0xf040a0d0,

	0xbcd001c7,

	0x0721f500,

	0x010c9202,

	0xf000acd0,

	0xbcd002c7,

	0x0721f500,

	0x2621f502,

	0x8087f102,

	0x0684b608,

	0xb70089cf,

	0x95220080,

/* 0x02ba: ctx_init_strand_loop */

	0x8ed008fe,

	0x408ed000,

	0xb6808acf,

	0xa0b606a5,

	0x00eabb01,

	0xb60480b6,

	0x1bf40192,

	0x08e4b6e8,

	0xf1f2efbc,

	0xb6085c87,

	0x94bd0684,

	0xd00399f0,

	0x00f80089,

/* 0x02ec: error */

	0xe7f1e0f9,

	0xe3f09814,

	0x8d21f440,

	0x041ce0b7,

	0xf401f7f0,

	0xe0fc8d21,

/* 0x0306: init */

	0x04bd00f8,

	0xf10004fe,

	0xf0120017,

	0x12d00227,

	0x3e17f100,

	0x0010fe04,

	0x040017f1,

	0xf0c010d0,

	0x12d00427,

	0x1031f400,

	0x060817f1,

	0xcf0614b6,

	0x37f00012,

	0x1f24f001,

	0xb60432bb,

	0x02800132,

	0x04038003,

	0x040010b7,

	0x800012cf,

	0x27f10002,

	0x24b60800,

	0x0022cf06,

/* 0x035f: init_find_chipset */

	0xb65817f0,

	0x13980c10,

	0x0432b800,

	0xb00b0bf4,

	0x1bf40034,

/* 0x0373: init_context */

	0xf100f8f1,

	0xb6080027,

	0x22cf0624,

	0xf134bd40,

	0xb6070047,

	0x25950644,

	0x0045d008,

	0xbd4045d0,

	0x58f4bde4,

	0x1f58021e,

	0x020e4003,

	0xf5040f40,

	0xbb013d21,

	0x3fbb002f,

	0x041e5800,

	0x40051f58,

	0x0f400a0e,

	0x3d21f50c,

	0x030e9801,

	0xbb00effd,

	0x3ebb002e,

	0x0040b700,

	0x0235b613,

	0xb60043d0,

	0x35b60825,

	0x0120b606,

	0xb60130b6,

	0x34b60824,

	0x022fb908,

	0x026321f5,

	0xf1003fbb,

	0xb6080017,

	0x13d00614,

	0x0010b740,

	0xf024bd08,

	0x12d01f29,

/* 0x0401: main */

	0x0031f400,

	0xf00028f4,

	0x21f41cd7,

	0xf401f439,

	0xf404e4b0,

	0x81fe1e18,

	0x0627f001,

	0x12fd20bd,

	0x01e4b604,

	0xfe051efd,

	0x21f50018,

	0x0ef404c3,

/* 0x0431: main_not_ctx_xfer */

	0x10ef94d3,

	0xf501f5f0,

	0xf402ec21,

/* 0x043e: ih */

	0x80f9c60e,

	0xf90188fe,

	0xf990f980,

	0xf9b0f9a0,

	0xf9e0f9d0,

	0x800acff0,

	0xf404abc4,

	0xb7f11d0b,

	0xd7f01900,

	0x40becf1c,

	0xf400bfcf,

	0xb0b70421,

	0xe7f00400,

	0x00bed001,

/* 0x0474: ih_no_fifo */

	0xfc400ad0,

	0xfce0fcf0,

	0xfcb0fcd0,

	0xfc90fca0,

	0x0088fe80,

	0x32f480fc,

/* 0x048f: hub_barrier_done */

	0xf001f800,

	0x0e9801f7,

	0x04febb00,

	0x9418e7f1,

	0xf440e3f0,

	0x00f88d21,

/* 0x04a4: ctx_redswitch */

	0x0614e7f1,

	0xf006e4b6,

	0xefd020f7,

	0x08f7f000,

/* 0x04b4: ctx_redswitch_delay */

	0xf401f2b6,

	0xf7f1fd1b,

	0xefd00a20,

/* 0x04c3: ctx_xfer */

	0xf100f800,

	0xb60a0417,

	0x1fd00614,

	0x0711f400,

	0x04a421f5,

/* 0x04d4: ctx_xfer_not_load */

	0x4afc17f1,

	0xf00213f0,

	0x12d00c27,

	0x0721f500,

	0xfc27f102,

	0x0223f047,

	0xf00020d0,

	0x20b6012c,

	0x0012d003,

	0xf001acf0,

	0xb7f002a5,

	0x50b3f000,

	0xb6000c98,

	0xbcbb0fc4,

	0x010c9800,

	0xf0020d98,

	0x21f500e7,

	0xacf0015c,

	0x04a5f001,

	0x4000b7f1,

	0x9850b3f0,

	0xc4b6000c,

	0x00bcbb0f,

	0x98050c98,

	0x0f98060d,

	0x00e7f104,

	0x5c21f508,

	0x0721f501,

	0x0601f402,

/* 0x054b: ctx_xfer_post */

	0xf11412f4,

	0xf04afc17,

	0x27f00213,

	0x0012d00d,

	0x020721f5,

/* 0x055c: ctx_xfer_done */

	0x048f21f5,

	0x000000f8,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,